8051
AVR
EZLab
PIC
80C196KC
DSP
ARM
VHDL
ũθ콺
κ౸
Battle κ
κȸ
޸շκ
Embeded Linux
HW/SW
RTOS
 
 

2. 196

 

II. 196 Assember

II-II. 196

II-II-4. (Logical) Shift

196KC shift ̴.

mnemonic

byte

state

operand

flags

1st

2nd

3rd

Z

N

C

V

VT

ST

AND

2+BEA

4+CEA

wreg

waop


0

0



AND

3+BEA

5+CEA

Dwreg

Swreg

waop

0

0



ANDB

2+BEA

4+CEA

breg

waop


0

0



ANDB

3+BEA

5+CEA

Dbreg

Swreg

waop

0

0



OR

2+BEA

4+CEA

wreg

waop


0

0



ORB

2+BEA

4+CEA

breg

baop


0

0



XOR

2+BEA

4+CEA

wreg

waop


0

0



XORB

2+BEA

4+CEA

breg

baop


0

0



NOT

2

4

wreg



0

0



NOTB

2

4

breg



0

0



SHL

3

7+No.

wreg

cnt/breg


?


SHR

3

7+No.

wreg

cnt/breg


0


SHLB

3

7+No.

breg

cnt/breg


?


SHRB

3

7+No.

breg

cnt/breg


0


SHLL

3

7+No.

lreg

cnt/breg


?


SHRL

3

7+No.

lreg

cnt/breg


0


SHRA

3

7+No.

wreg

cnt/breg



SHRAB

3

7+No.

breg

cnt/breg



SHRAL

3

7+No.

lreg

cnt/breg



NORMAL

3

11+No.

lreg

breg


?

0




 

< ǥ ִ operand ǹ>

cnt : 0~15 . No. : shift

II-II-4-1.

196 ɿ AND, OR, XOR, NOT , ϸ C, V flag clearȴ.

(1) AND/ANDB (logical AND in word/byte)

AND ɿ 2 operand ִ ɰ 3 operand ִ ִ.

1> AND/ANDB <1st operand>, <2nd operand> ; <1st op> <1st op> AND <2nd op>

2> AND/ANDB <1st op>, <2nd op>, <3rd op> ; <1st op> <2nd op> AND <3rd op>

ex) AND 40H, #0FF00H ; [40H] [40H] AND FF00H (word)

address

low byte

high byte

Z

N

C

V

VT

ST

40H

78H

56H







40H

00H

56H

0

0

0

0



 

ANDB 40H, 50H, 6100H[0] ; [40H] [50H] AND [6100H] (byte)

address

data

Z

N

C

V

VT

ST

6100H

A8H







50H

85H

40H

??

6100H

A8H

0

1

0

0



50H

85H

40H

80H

 

, AND register Ư Ʈ 0 ִ.

) 50H 4, 5 bit 0

ANDB 50H, #11001111B ; 50H bit4, 5 clear.

(2) OR/ORB (logical OR in word/byte)

OR ɿ operand ִ.

> OR/ORB <1st operand>, <2nd operand> ; <1st op> <1st op> OR <2nd op>

ex) ORB 50H, 60H ; [50H] [50H] OR [60H] (byte)

address

data

Z

N

C

V

VT

ST

60H

85H







50H

77H

60H

85H

0

1

0

0



50H

F7H

 

AND ϰ, OR Ư bit 1 ִ.

) 50H 1, 2, 7 bit 1

ORB 50H, #10000110B ; 50H bit1, 2, 7 set

(3) XOR/XORB (logical eXclusive OR in word/byte)

OR ϴ. XOR Ư bit toggle ϰ 1 Ư bit XOR ϸ ȴ.( 1 XOR 0 = 1, 1 XOR 1 = 0, 0 XOR 0 = 0, 0 XOR 1 = 1)

> XOR/XORB <1st operand>, <2nd operand> ; <1st op> <1st op> XOR <2nd op>

ex) XOR 40H, [50H]+ ; [40H] [40H] XOR ([50H] Ű memory ) (word)

; [50H] [50H] + 2

address

low byte

high byte

Z

N

C

V

VT

ST

7256H

8FH

54H







50H

56H

72H

40H

36H

C9H

7256H

8FH

54H

0

1

0

0



50H

58H

72H

40H

B9H

9DH

 

XOR Ư bit toggle(01, 10) ִ.

) 50H 3, 4, 6 bit toggleϰ

XORB 50H, #01011000B ; 50H bit3, 4, 6 toggle

(4) NOT/NOTB (logical NOT in word/byte)

byte/word complementϴ ̴. bit .

> NOT/NOTB <word/byte register>

ex) NOTB 60H

address

data

Z

N

C

V

VT

ST

60H

85H







60H

7AH

0

0

0

0



 

NOT 70H

address

low byte

high byte

Z

N

C

V

VT

ST

70H

FFH

FFH







70H

00H

00H

1

0

0

0



 

II-II-4-2. Shift

Shift 8/16/32 bit data ѹ ڸ ̵ϴ ̸, ڸ ̵ counter data(0~15) ǥ ְ, byte register(count 16~255) ̿ ִ.

(1) SHL/SHLB/SHLL (Shift left in word/byte/long)

ŭ shiftϴ ̴. ֻ bit C flag ä ǰ, bit 0 ä ȴ. 1bit shift left ×2 ɰ .

 

C


operand




0

 

> SHL/SHLB/SHLL <word/byte/long register>, #data

SHL/SHLB/SHLL <word/byte/long register>, <byte register>

ex) SHL 50H, #2 ; [50H] word 2bit shift

address

low byte

high byte

Z

N

C

V

VT

ST

50H

3DH

53H







50H

F4H

4CH

0

-

1

0

0

-

 

(2) SHR/SHRB/SHRL (Shift right in word/byte/long)

ŭ shiftϴ ̴. bit C flag ä ǰ, ֻ bit 0 ä ȴ. shift right ÷2 ɰ . , ST bit clearǰ, shift right ϴ C flag 1 shift Ǹ setȴ.

 



operand


C

0


 

> SHR/SHRB/SHRL <word/byte/long register>, #data

SHR/SHRB/SHRL <word/byte/long register>, <byte register>

ex) SHR 50H, #4 ; [50H] word 4bit shif

address

low byte

high byte

Z

N

C

V

VT

ST

50H

CDH

ABH







50H

BCH

0AH

0

0

1

0


1

 

(3) SHRA/SHRAB/SHRAL

ŭ shiftǸ, bit C flag shiftǰ, ֻ bit ֻ bit rotateȴ. , 1bit shift signed data ÷2 ȴ. ST flag Ѵ.

 


operand


C



 

> SHRA/SHRAB/SHRAL <word/byte/long register>, #data

SHRA/SHRAB/SHRAL <word/byte/long register>, <byte register>

ex) SHRAB 41H, #3

address


Z

N

C

V

VT

ST

41H

F0H







41H

F2H

0

0

1

0


1

 

II-II-4-3. Normalize

Nomalize long-integer operand normalizeѴ. , ֻ bit 1 shift leftѴ. 0~31 shift ϴ ؼ ֻ bit 1̸, ǰ Z flag setȴ. shift byte operand ȴ.

: http://www.postech.ac.kr/group/poweron/ - lectures/Micro processor, controller, Ƹ

: Micro controller 80196 ʺ -



 

ȣ : () κ ڵϹȣ:214-86-56219 ǸžŰ19-2544 ǥ: Ŵ뼷 ȭ:(02)2679-8556 Fax :(02)2679-8557
: ⵵ õ ̱ 뵿 õ ũũ 401 502ȣ     繫 : 4 8-1 4
Copyright(C) 2004, () κ ý All Rights Reserved E-Mail : WebMaster