8051
AVR
EZLab
PIC
80C196KC
DSP
ARM
VHDL
ũθ콺
κ౸
Battle κ
κȸ
޸շκ
Embeded Linux
HW/SW
RTOS
 
 


2. 196

 

II. 196 Assember

II-II. 196

II-II-3. (compare) ɰ Branch

program ٲٴ branch ɰ loop ɿ ˾ƺڴ. branch ( branch) ȿ ϱ ؼ 񱳸ɵ Բ ˾ƺ ̴. 196KC branch ũ ִ.

branch

branch

branch

Ư bit test branch

Ư branch

ǥ 196KC ɰ branch ̴.

<Ʒ ǥ ִ operand ǹ>

disp : (displacement) byte(-128~+127)

ival : immediate value

A/B : "A" (jump was not taken), "B" (jump was taken) branch state

xxx : ɾ ؼ ä address bbb : bit

< >

mnemonic

byte

state

operands

flags

1st

2nd

Z

N

C

V

VT

ST

CMP

2+BEA

4+CEA

wreg

waop


CMPB

2+BEA

4+CEA

breg

baop


CMPL

3

7

lreg

lreg


 

<branch >

mnemonic

byte

state

flags

76543210

1st

2nd

3rd

Z

N

C

V

VT

ST

LJMP

3

8

11100111

disp-high

disp-low








SJMP

2

8

00100xxx

disp-low









BR

2

8

11100011

wreg









JC

2

4/8

11011011

disp









JNC

2

4/8

11010011

disp









JH

2

4/8

11011001

disp









JNH

2

4/8

11010001

disp









JE

2

4/8

11011111

disp









JNE

2

4/8

11010111

disp









JV

2

4/8

11011101

disp









JNV

2

4/8

11010101

disp









JGE

2

4/8

11010110

disp









JLT

2

4/8

11011110

disp









JVT

2

4/8

11011100

disp









JNVT

2

4/8

11010100

disp









JGT

2

4/8

11010010

disp









JLE

2

4/8

11011010

disp









JST

2

4/8

11011000

disp









JNST

2

4/8

11010000

disp









JBC

3

5/9

00110bbb

disp

breg








JBS

3

5/9

00111bbb

disp

breg








DJNZ

3

5/9

11100000

disp

breg








DJNZW

3

5/10

11100001

disp

wreg








NOP

1

4

11111101










SKIP

2

4

00000000

breg









TIJMP

4

13+5

11100010

wreg1

wreg2

ival








II-II-3-1.

CMP/CMPB (Compare in word/byte)

꿡 ϰ, branch ظ Ѵ. operand ϰ flag ȭŰ Ѵ. , ɵ 1st operand 2nd operand flag ְԵǸ, Ŀ operand ʴ´.

> CMP/CPMB/CMPL <1st operand>, <2nd operand>

; 1st op word/byte/long register 2nd op operand Ѵ.

2nd operand direct, indirect, immediate addressing ϳ, long register direct ϴ.

ex) CMP 40H, 50H ; [40H] - [50H] Ͽ (word), flagȭ

 

address

low byte

high byte

Z

N

C

V

VT

ST

50H

34H

12H







40H

78H

56H

50H

34H

12H

0

0

0

0

0


40H

78H

56H

 

(5678H - 1234H = 4444H)

CMPB 50H, #'A' ; [50H] - 41H('A' ASCII code) Ͽ (byte)

address


Z

N

C

V

VT

ST

50H

34H







50H

34H

0

1

0

0

0


 

(34H - 41H = F3(-DH))

II-II-3-2. branch

б ̳ bit ʰ α׷ ٲٴ ̴. 196KC branchμ LJMP SJMP ִ. ׷ (absolute) branch . jump ̶ ؾ Ѵ. ׷ assembler ֹǷ α׷ label ϸ ȴ.

(1) LJMP (Long Jump)

ġ -32768~+32767 jump ִ.

> LJMP <displacement word>

<displacement word> jump ( ġ) ϸ, IP(instruction pointer) ġ -32768~+32767 (196KC address space) б ִ. address ƴ .

ex) (2) SJMP (Short Jump)

ġ -1024~+1023 (1K) б ִ. ̴ jump 1K ִ ִ. ̷ LJMP , code SJMP LJMP 1byte ۱ memory ִ.

> SJMP <displacement 11bit>

displacement 11bit CPU address ȣ ȮϿ 16bit Ѵ.

ex)

address code line program source code

8328 2000 263 SJMP EEE

264

832A CC1A 265 EEE: POP AX

832C F5 266 POPA

line 263 code 2000H ǹ

20H=00100000B 00100XXX SJMP code̴.

20H=00100000B 3bit 000B operand 00H (832AH - 832AH) ǹѴ.(00H = 000 00000000B, 11bit - mnemonic operand ԵǾִ.) 'SJMP EEE' IP jump address Ƿ(832AH) 0 ȴ.

address code line program source code

8220 124 MAIN1:

125 ; CALL delay400m

126

8220 27FE 127 SJMP MAIN1

line 127 code 27FEH ǹ

27H=00100111B 00100XXX SJMP code

27H=00100111B 111B(=7H) operand FEH (8220H - 8222H = 7FEH (-2H)), 11bit displacement) ǹѴ.

(3) NOP (No Operation)

NOP ƹ ͵ ʴ ̸ CPU ¿ ʴ´. NOP . operands ʿ .

program ش.

debug ϴ.

program NOP code ä program ִ.

ܺ IO ʿϴ.

> NOP

address

code

line

program

source

code

 

 

 

 

79

 

 

 

 

 

800C

 

80

CSEG

AT

800CH

 

; HSO interrupt

800C

E79D02

81

 

 

LJMP

HSO_SERVICE

 

 

:

:

 

:

 

:

:

 

:

:

 

:

 

:

:

82A6

4500010A04

205

 

 

ADD

HSO_TIME, TIMER1, #100H

82AB

F0

206

 

 

RET

 

 

 

 

207

 

 

 

 

 

82AC

F4

208

HSO_SERVICE:

PUSHA

 

; make motor clock

82AD

C81A

209

 

 

PUSH

AX

 

82AF

B0171B

210

 

 

LDB

AH, IOS2

 

α׷ line 81 code E79D02 ǹ̴ .

E7 : LJMP code( table 11100111B)

9D02 : operands, 9DH low byte, 02H high byte̹Ƿ, ǹϴ 029DH̴. ̴ HSO_SERVICE ȴ.(82ACH - 800FH)

α׷ memory Ǿ ְ ȴ.

address

data



:

:



82ADH

C8H



82ACH

F4H

HSO_SERVICE ġ

 

     (82ABH

     - 800FH)

 

82ABH

F0H


:

:


800FH

?

LJMP HSO_SERVICE IP ġ

800EH

02H



800DH

9DH



800CH

E7H



:

:

 

(2) SJMP (Short Jump)

ġ -1024~+1023 (1K) б ִ. ̴ jump 1K ִ ִ. ̷ LJMP , code SJMP LJMP 1byte ۱ memory ִ.

> SJMP <displacement 11bit>

         displacement 11bit CPU address ȣ ȮϿ 16bit Ѵ.

ex)

address

code

line

program

source

code

 

8328

2000

263

 

 

SJMP

EEE

 

 

264

 

 

 

 

832A

CC1A

265

EEE:

 

POP

AX

832C

F5

266

 

 

POPA

 

line 263 code 2000H ǹ

20H=00100000B 00100XXX SJMP code̴.

20H=00100000B 3bit 000B operand 00H (832AH - 832AH) ǹѴ.(00H = 000 00000000B, 11bit - mnemonic operand ԵǾִ.) 'SJMP EEE' IP jump address Ƿ(832AH) 0 ȴ.

address

code

line

program

source

code

 

8220

 

124

MAIN1:

 

 

 

 

 

125

;

 

CALL

delay400m

 

 

126

 

 

 

 

8220

27FE

127

 

 

SJMP

MAIN1

line 127 code 27FEH ǹ

27H=00100111B 00100XXX SJMP code

27H=00100111B 111B(=7H) operand FEH (8220H - 8222H = 7FEH (-2H)), 11bit displacement) ǹѴ.

(3) NOP (No Operation)

NOP ƹ ͵ ʴ ̸ CPU ¿  ⵵ ʴ´. NOP . operands ʿ .

program ش.

debug ϴ.

program NOP code ä program ִ.

ܺ IO ⿡ ʿϴ.

> NOP

(4) SKIP (2 byte NOP)

2 byte NOP ɰ . byte register ̸ .() NOP 뵵̴.

> SKIP <byte operand>

II-II-3-3. branch

տ branch ɿ ˾ƺҴ. branch б ޸ ǿ бϴ ̴. flag ¸ ̿Ͽ ľѴ. compare ڿ бⰡ ̴. ( ũ⸦ ϱ ؼ) Ư flag testϿ б ִ. ̷ ɵ conditional jump Ѵ. conditional jump 1byte(-128~+127) ѵǾ ִ.

б⿡ ȣ ִ (signed) , ƴϸ ȣ (unsigned) .

unsigned

used flags

signed

used flags

N

Z

C

Z

JLT (Less Than)

1

X

JH (Higher)

1

0

JLE (Less or Equal)

1

1

JNH (Not Higher)

0

1

JGE (Great or Equal)

0

X




JGT (Greater Than)

0

0




 

, flag ̸ branch ɵ ִ.

flag

1 branch

0 branch

Z

JE (Equal)

JNE (Not Equal)

C

JC (Carry is set)

JNC (Carry is Not set(clear))

V

JV (overflow is set)

JNV (V flag is clear)

VT

JVT (VT flag is set)

JNVT (VT flag is clear)

ST

JST (ST flag is set)

JNST (ST flag is clear)

 

ɵ Ƿ ⿡ ʱ Ѵ. ɵ ̴.

> JXX <diplacement 8bit>

ex) <program example 1>

L13;

CMPB

SPTEMP, #'a'

; [SPTEMP] a ASCII ([SPTEMP] - #'a')(byte)

 

JNE L

L14

; (if Z=1, if SPTEMP#'a') jump to 'L14'

 

LJMP

ABOUT

; Long jump to 'ABOUT'

L14;

CMPB

SPTEMP, #CR

; [SPTEMP] CR(\n) ASCII (]SPTEMP] - #CR)

 

JE

MAINL

; (if Z=0, if [SPTEMP]=#CR) jump to 'MAINL'

L15:

LD

MSG_ADDR, #MNOT_DEF_KEY

; [MSG_ADDR]MNOT_DEF_KEY (word addr)

 

CALL

PUT_STRING

; Call PUT_STRING routine

 

SJMP

MAINL

; Short jump to 'MAINL'

<program example 2> - Let's interpret it....

THAN:

CMP

TARGET_SPD_L, MOTOR_SPEED_L

 

JE

CHECK

 

SJMP

EPOSC

CHECK:

SUBB

AH, SEN_VAL1, SEN_VAL3

 

CMPB

AH, #50

 

JGT

MUST3

 

CMPB

AH, #25

 

JGT

MUST2

 

CMPB

AH, #8

 

JGT

MUST1

 

CMPB

AH, #-50

 

JLT

MUST3

 

CMPB

AH, #-25

 

JLT

MUST2

 

CMPB

AH, #-8

 

JLT

MUST1

 

SJMP

EPOSC

MUST1:

CMPB

SEN_VAL1, SEN_VAL3

 

JH

ILEFT1

 

ADD

TARGET_SPD_R, #20

 

CALL

DELAY25M

 

SUB

TARGET_SPD_R, #20

 

SJMP

EPOSC

II-II-3-4. Ư bit test branch

Ư register bit testϴ ̴.(set or clear?) 1byte ѵǾ ִ. 8bit register ϹǷ bit ȣ 0~7 ѵǾ ִ.

> JBS <byte register>, <bit number>, <displacement byte> ; Jump if Bit is Set

         JBC <byte register>, <bit number>, <displacement byte> ; Jump if Bit is Clear

ex)

PUTLED:

 

PUTLED:

CH, IOPORT2

; CH : current PORTX data

 

 

JBS

H, 0, PUL1

; AH : input LED data

 

 

ANDB

CH, #11110111B

 

 

 

SJMP

PUL2

 

 

PUL1:

ORB

CH, #00001000B

 

 

PUL2:

JBS

AH, 1, PUL3

 

 

 

ANDB

CH, #11101111B

 

 

 

SJMP

PUL4

 

II-II-3-5. Ư Branch

DJNZ/DJNZW (Decrease and jump if zero in word/byte)

byte word register -1ϰ 0 ƴϸ branchϰ, ׷ ϴ ̴. 1byte̸ byte/word register counter Ѵ. ϸ, 񱳸ɰ branch , counter ϳ ִ. 196 ִ. (96 .)

> DJNZ/DJNZW <byte/word register>, <displacement byte>

         ; [breg][breg]-1, if [breg]0 jump to indicated location(-128~+127 range)

ex)

DELAY: PUSH AX ; 90 ms Delay

LD AX, #0F000H ; [AX][AX]-1

DY1: NOP ; no operation

DJNZW AX, DY1 ; AX 1ҽŰ AX=0̸ , 1̸ DY1 jump

POP AX

RET

DELAY:

 

PUSH

AX

; 90 ms Delay

 

 

LD

AX, #0F000H

; [AX][AX]-1

 

DY1:

NOP

 

; no operation

 

 

DJNZW

AX, DY1

; AX 1ҽŰ AX=0̸ , 1̸ DY1 jump

 

 

POP

AX

 

 

 

RET

 

 

α׷ DJNZW ̿ؼ delay α׷̴. AX register F000H=61440̹Ƿ, DY1 loop 61440 ݺϰ ȴ. ׸, NOP ð 4 state time, DJNZW ð(jump was taken) 10 state time ̹Ƿ, loop ϴ ð 14 state time ȴ. ð 14 state time * 61440 ̹Ƿ, clock=20M 14×2×1/20M×61440 =86.0 ms delay ȴ.

II-II-3-6. branch

branch ɵ branch ̴. program ѹ branch . branch α׷ ߿ software branch ִ. (Ư ġ ϰ ϸ ̴.)

(1) BR (Branch indirect)

> BR <word register> ; register Ű branch

ex)

BR_ADDR

EQ          40H

; BR_ADDR

 

:

:

 

 

 

LD

BR_ADDR, #5000H

; [BR_ADDR] #5000H

 

BR

[BR_ADDR]

 

; 5000H branch

:

:

:

 

 

CSEG

AT

5000H

 

 

WAIT:

SJMP

WAIT

 

 

(2) TIJMP (Table Indirect Jump)

address table ߿ õ address branchϴ ̴. BR ϳ, branch address table ã´ٴ ٸ.

> TIJMP <word register>, [word register], (#mask byte)

⼭ 1st operand address table base Ű word register̴.

2nd operand 8bit index Ǿ ִ Ű word register̴.

3rd operand index AND ؼ jump address Ǿ ִ ϱ data̴.(immediate value)

destination .

destination = 2×offset + [base], offset = [index](AND)mask

ex)

WR1 EQU 60H

WR2 EQU 80H

JUMP1 EQU 0F000H

JUMP2 EQU 0B000H

JUMP3 EQU 9000H

: : :

ORG 8200H

LD WR1, #JUMP_TABLE ; [WR1]jump address table base address

LD WR2, #INDEX_DATA ; [WR2]index data ִ base address

TIJMP WR1, [WR2], #00000011B ; JUMP3(9000H) branch

: : : :

JUMP_TABLE: DCW JUMP1 ; jump address table(word )

DCW JUMP2

DCW JUMP3

: : : :

INDEX_DATA: DCB 2 ; index data table

DCB 1

DCB 0


WR1

EQU

60H

 

 

WR2

EQU

80H

 

 

JUMP1

EQU

0F000H

 

 

JUMP2

EQU

0B000H

 

 

JUMP3

EQU

9000H

 

 

:

:

:

 

 

ORG

8200H

 

 

 

 

 

LD

WR1, #JUMP_TABLE

; [WR1]jump address table base address

 

 

LD

WR2, #INDEX_DATA

; [WR2]index data ִ base address

 

 

TIJMP

WR1, [WR2], #00000011B

; JUMP3(9000H) branch

:

:

:

:

 

JUMP_TABLE:

DCW

JUMP1

; jump address table(word )

 

 

DCW

JUMP2

 

 

 

DCW

JUMP3

 

:

:

:

:

 

INDEX_DATA:

DCB 2

 

; index data table

 

 

DCB 1

 

 

 

 

DCB

 

 

    : http://www.postech.ac.kr/group/poweron/ - lectures/Micro processor, controller, Ƹ

    : Micro controller 80196 ʺ -

<Programming Exercise>

1.   α׷ мغ.

('A' ASCII code 41H, 'G' 47H, '0' 30H, '9' 39H̴. DCB 0F7H TRAP code̴. ⿡ ϰ .(RET̶ ص ȴ.))

< 1>

BR1 

 EQU 

 40H

 

:

:

:

:

CSEG

AT

4000H

 

 

 

CMPB

BR1, #'0'

 

 

JNC

NOT_HEX

 

 

CMPB 

 BR1, #'G'

 

 

 JC 

 A_HEX2

A_HEX1:

ANDB

BR1, #0F

 

 

 

CLRC

 

DCB

0F7H

 

 

A_HEX1:

CMPB

BR1, #'A'

 

 

 

JNC

NOT_HEX

 

 

CMPB

BR1, #'G'

 

 

JC

NOT_HEX

 

 

SUBB

BR1, #7

 

 

SJMP 

A_HEX1

NOT_HEX:

 

 SETC

 

DCB

0F7H

 

 

END

 

 

 

< 2>

RSEG      AT

0020H

 

RESULT_LOW: 

DSL

1

RESULT_HIGH:

DSL

1

RESULT_W0 

EQU 

RESULT_LOW

RESULT_W1

EQU 

RESULT_LOW+2

RESULT_W2

EQU 

RESULT_HIGH

RESULT_W3

EQU 

RESULT_HIGH+2

 

TEMP

 

DSL

1

TEMP_L

 

EQU

TEMP

TEMP_H 

 

EQU

TEMP+2

 

OPE_A:

 

DSL

1

OPE_A_L

 

EQU 

 OPE_A

OPE_A_H

 

EQU 

OPE_A+2

 

OPE_B:

 

DSL

1

OPE_B_L

 

EQU 

OPE_B

OPE_B_H 

 

EQU 

OPE_B+2

:             :

:

:            :

CSEG     AT 

8000H

 

 

 

MULU 

RESULT_LOW, OPE_A_L, OPE_B_L

 

 

MULU 

RESULT_HIGH, OPE_A_H, OPE_B_H

 

 

MULU 

TEMP, OPE_A_H, OPE_B_L

 

 

ADD

RESULT_W1, TEMP_L

 

 

ADDC

RESULT_W2, TEMP_H

 

 

ADDC

RESULT_W3, #0

 

 

MULU

TEMP, OPE_A_L, OPE_B_H

 

 

ADD

RESULT_W1, TEMP_L

 

 

ADDC

RESULT_W2, TEMP_H

 

 

ADDC

RESULT_W3, #0

 

 

RET

 

END

 

 

 

2. ĭ ä

< 3>

ɾ

20H

21H

flags

(low byte)

(high byte)

Z

N

V

VT

C

ST

CLR 20H









ADD 20H, #4789H









ADDC 20H, #6488H









ADDB 20H, #88H









ADDCB 20H, #33H









SUB 20H, #3567H









SUBC 20H, #8000H









SUBB 20H, #45H









SUBCB 20H, #78H









LDB 20H, #0FFH









INCB 20H









DECB 20H









LDB 20H, #0FFH









INCB 20H









DECB 20H









EXTB 20H









NEG 20H









 

< 4>

ɾ

20H

21H

24H

25H

2CH

2DH

flags

Z

N

V

VT

C

ST

CLR 20H













LD 24H, #0AAAAH













LD 2CH, #5555H













CMP 24H, 2CH













ADD 20H, 24H, 2CH













SUB 20H, 2CH, 24H













CMPB 21H, 2DH













LDB 24H, #0BAH













ADDB 20H, 24H, #39H













SUBB 20H, 24H, #0ABH













MULB 24H, 2CH













LDBSE 20H, 21H













LDBZE 2CH, 25H













CMP 20H, 24H













SETC













 

3. ߸ ? Ʋ غ.

< 5>

LDB 56H, [87H]+

SUBC 40H, 50H, #30H

ADDB [67H], #60H, 50[50H]

LDBZE 45H, 50H

JBS 50H, 8, XX

DJNZ 55H, LOOP

ST 55H, 50H[0]

MUL 52H, 50H, #40

CMP 50H, [60H]




 

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