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80C196KC
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2. 196

 

II. 196 Assember

II-II. 196

II-II-1.

II-II-1-2 (addressing mode)

*******************************************************

< ǥ >

- ǥ Sign&Magnitude, 1's complement, 2's complement ִµ, Ư¡ MSB Ѵٴ ̴. , MSB 1̸ , 0̸ ȴ. Ư¡ 캸 .

* Sign & Magnitude

- ȣ ũⰡ Ǿ ִ. MSB sign̰ bit magnitude̴. δ , ؼ ȸΰ ʿϹǷ ӵ ʴ ̴.

-> ex) 34D = 0010 0010B, -33D = 1010 0001B

* 1's complement

- sign & magnitude bit complement ϴ ̴. ʴ ̴.

-> ex) - 34D = 1101 1101B

* 2's complement

- İ , 1's complement ó bit complement 1 ָ ȴ. 8bit number system,

-19D = complement(0001 0011) + 1 = 1110 1100 + 1 = 1110 1101 = 0EDH

16bit

-255D = complement(0000 0000 1111 1111) + 1 = 1111 1111 0000 0001 = 0FF01H

ȴ.

n bit system -~ -1 Ÿ ִ.

digital system(processor, conroller,...) Ѵ.

*********************************************************

(5) short index

İ ϳ 8bit index(offset) Բ ؼ memory ּҸ . ̶ index 8bit ȣ ִ (-128(80H)~+127(7FH))ȴ. index [ ] տ ָ ȴ.

2 operand : (signed byte number(offset))[(word pointer in register file)]

                                ex) LD 70H, 50H[60H]

                                    (  )

:


61H

90H

high byte

60H

10H

low byte

:

:


:

:


71H

??

high byte

70H

??

low byte

6FH

:


ּ


:

:

9061H

99H

9060H

88H

:

:

9011H

33H

9010H

22H

:

:

          ; 60H word register 50H address

          ; memory 70H word Ѵ.

                                     ( )

ּ

:


61H

90H

high byte

60H

10H

low byte

:

:


:

:


71H

99H

high byte

70H

88H

low byte

6FH

:


ּ


:

:

9061H

99H

9060H

88H

:

:

9011H

33H

9010H

22H

:

:

 

               LDB 70H, -5[60H]

                (  )

ּ

:

61H

90H

60H

18H

:

:

:

:

71H

:

70H

18H

6FH

:

ּ


:

:

9018H

88H

9017H

77H

9016H

66H

9015H

55H

9014H

44H

9013H

33H

60H Ű ּҿ -5 ּҸ memory

; 70H byte Ѵ.

                  ( )

ּ

:

61H

90H

60H

18H

:

:

:

:

71H

:

70H

33H

6FH

:

ּ


:

:

9018H

88H

9017H

77H

9016H

66H

9015H

55H

9014H

44H

9013H

33H

ST 70H, -100[80H] ; 70H word 80H Ű ּ -100 ּ

; memory Ѵ. 70H <= [80H]-100

STB 80H, 80[90H]

(6) long index

short index , index 8bit ƴ϶ 16bit ȣ ִ(signed) (-32768~+32767) ȴ. ϴ.

2 operand : (signed word number(offset))[(word pointer in register file)]

ex) LD 60H, 4000H[60H] ; 60H Ű ּҿ 4000H ּҸ

; memory 60H word Ѵ.

           STB 70H, 0FF00H[60H]

                  (  )

ּ

:

61H

95H

60H

06H

:

:

:

:

71H

:

70H

18H

6FH

:

ּ


:

:

9506H

??

9505H

??

:

:

9407H

??

9406H

??

:

:

 

; 70H word 60H Ű ּҿ 0FF00H

; (-100H) ּҸ memory byte Ѵ.

                   (  )

ּ

:

61H

95H

60H

06H

:

:

:

:

71H

:

70H

18H

6FH

:

ּ


:

:

9506H

??

9505H

??

:

:

9407H

??

9406H

18H

:

:

(7) zero register

zero register long index addressing ϴ. ׷ Ǵ register zero register(SFR 0H : register R0) Ǿ ִٴ ٸ. , zero register ׻ 0 Ǿ Ƿ, offset ̿ؼ (register direct addressing) ְ ȴ. , ܺ memory IO, RAM access ְ ȴ. (տ, ܺθ accessϱ ؼ indirect addressing ؾ Ѵٰ ߴ.)

2 operand : (signed word(or byte) number(offset))[0]

ex) LD 80H, 5432H[0] ; 5432H 80H word Ѵ.

; (0 ׻ 0 Ǿֱ )

STB 80H, 4321H[0] ; 80H 4321H byte Ѵ.

STB 90H, 120H[0]

(8) Stack pointer register

stack pointer Ѵ. short, long index ִ.

2 operand : (signed word(or byte) number(offset))[SP]

ex) LD 80H, 100H[SP] ; Stack Pointer Ű ֿ 100H ּҸ

; memory 80H word Ѵ.

(9) RAM 256byte(100H~1FFH) ϴ

տ RAM 232 byte register file ̳ 꿡 ִٰ ߴ. ׷ٸ RAM ?

RAM registeró ϴ. ׷ window ̿Ͽ Ư register file mapping Ѽ ؾ Ѵ. տ ٽ 캸.

window ϱ ؼ WSR(Window Select Register) Ѵ. WSR õǴ window̴.

* WSR (Window Select Register) window

 

7

6

5

4

3

2

1

0

function

X

0

0

0

0

0

0

0

window 0

X

0

0

0

0

0

0

1

window 1

X

0

0

0

1

1

1

1

window 15

X

1

0

0

X

X

X

X

window 32

X

0

1

0

0

X

X

X

window 64

X

0

0

1

0

0

X

X

window 128

 

̹ տ window . window SFR ٲٱ Ѵ. ׷ window 256 byte RAM ϱ Ѵ. ׸ WSR RAM register file Ư mappingǾ RAM register fileó ְ ȴ. 32byte window ũⰡ 32byte̹Ƿ 8, 64byte 64byte̹Ƿ 4, 128byte ũⰡ 128byte̹Ƿ 2 (window) ȴ. ̵ window register file mappingȴ. bit 7 DMA ϹǷ windowʹ . (X : don't care)

 

32byte window

64byte window

128byte window

WSR

base address

WSR

base address

WSR

base address

X100 1111

01E0H

X010 0111

01C0H

X001 0011

0180H

X100 1110

01C0H

X010 0110

0180H

X001 0010

0100H

X100 1101

01A0H

X010 0101

0140H

mapping

0080H

X100 1100

0180H

X010 0100

0100H



X100 1011

0160H

mapping

00C0H



X100 1010

0140H





X100 1001

0120H





X100 1000

0100H





mapping

00E0H





 

RAM 01C8H ϰ ʹٸ, WSR=X1001110B Ǿ ϰ(32 byte window ), 01C0H~01DFH register file 00E0H~00FFH mapping ǹǷ, 01C8 register file 00C8H accessϸ ̴. ̴ ִ.

II-II-1-3 ٸ data

(1) XCH/XCHB (eXCHange)

register ȯѴ. immediate, indirect addressing . ׷ Byte zero register addressing ִ.

>

XCH (word register), (word register)

XCHB (byte register), (byte register/zero register addressing)

ex) XCH 70H, 86H ; register 70H register 86H ٲ۴.(word)

XCHB 70H, 1860H[0] ; register 70H memory 1860H ٲ۴.(byte)

(2) LDBSE (LoaD Byte with Sign Extension) - Load integer with short integer

byte register ȣ ȮǾ word register ȴ. , byte register(2nd operand) 0 ̸̻(80H ) word register(1st operand) byte 0, 0 (80H ̸̻) word register byte FFH ȴ.

>

LDBSE (word register), (byte register)

ex) 60H(byte) => ȣȮ => 0060H(word) ; 96(decimal)

90H(byte) => ȣȮ => FF90H(word) ; -112(decimal)

(3) LDBZE (LoaD Byte with Zero Extension) - Load word with byte

byte register ȣȮ word register ȴ. , word register(1st operand) byte 0 ȴ.

>

LDBZE (word register), (byte register)

ex) LDBZE 50H, 80H                             

      (  )                

ּ

:

81H

11H

80H

22H

:

:

:

:

51H

:

50H

99H

4FH

:

 ; 80H byte register 50H word register ȣ

; Ȯ ȴ.

      (  )

ּ

:

81H

11H

80H

22H

:

:

:

:

51H

00H

50H

22H

4FH

:



(4) BMOVI (Block Move Interruptible)

memory ġ word data ٸ ġ block Ѵ. ̴ Ư memory block word data ٸ block ̴.

>

BMOVI (long register), (word register)

note>

1. 1nd operand long register ó source base address, destination base address , source/destination address ڵ ִ Ѵ.

2. 2nd operand Űܾ word counter̸, word counterŭ ۵ȴ.

3. block counter ϸ block counter ڵ ʱ DJNZ/DJNZW Ͽ Ѵ.

4. Ǵ interrupt ϴ. 80C196KC ̴.

ex) LD 60H, #3000H ; source base address

LD 62H, #8000H ; destination base address

LD 40H, #3 ; word counter

BMOVI 60H, 40H ; 1. [62H][60H]

; 2. [60H][60H]+2, [62H][62H]+2

; 3. [40H][40H]-1

, 3000H 3 word 8000H Ѵ.

                                                  ( BMOVI )

ּ

low byte

high byte


62H

00H

80H

destination base

60H

00H

30H

source base

:

:

:


42H

:

:


40H

03H

00H

block counter

3EH

:

:


:

:

:


ּ

low byte

high byte


8004H

?

?

destination

8002H

?

?

8000H

?

?

:

:

:


3004H

55H

66H

source

3002H

33H

44H

3000H

11H

22H

                                                 ( BMOVI )

ּ

low byte

high byte


62H

00H

80H

destination address

60H

00H

30H

source address

:

:

:


42H

:

:


40H

03H

00H

block counter

3EH

:

:


:

:

:


ּ

low byte

high byte


8004H

55H

66H

destination

8002H

33H

44H

8000H

11H

22H

:

:

:


3004H

55H

66H

source

3002H

33H

44H

3000H

11H

22H

II-II-2.

ɿ /, /, /, , branchɿ 캸 .

II-II-2-1. PSW(Program Status Word)

˾Ƶξ ִ. ٷ PSW(Program Status Word)̴. Ȥ 8x86 迭 flags Ѵ. PSW ̳ ɵ ݿѴ. (ٷ ) register мμ ִ. ϱ ؼ ݵ ̴ ˾Ƶξ Ѵ. PSW low byte interrupt mask register DZ high byte . flag condition flag Ѵ.

 

15

14

13

12

11

10

9

8

bit number

Z

N

V

VT

C

PSE

I

ST

flag

 

flag .

(1) I (Interrupt enable flag) : Interrupt /Ұ ϴ flag̰, NMI, TRAP, undefined OP code interrupt interrupt enable/disable Ѵ. EI(Enable Interrupt) DI(Disable Interrupt) ɿ ٲ ִ. I=1̸ enbale, I=0̸ disable ȴ.

(2) PSE (Peripheral transaction Server Enable) : PTS /Ұ ϴ flag̴. EPTS DPTS ̿ؼ ϸ PSE=1̸ enable, PSE=0̸ disableȴ.

(3) Z (Zero flag) : 0 Ÿ flag̴. 0̸ set(1), 0 ƴϸ clear(0)ȴ.

(4) C (carry flag) : MSB carry(ø ) setȴ. ׷ 꿡 borrow ߻ϸ clear(0), ߻ set(1) ȴ. ٸ CPUʹ Ʋ. shift ɿ shift bit carry flag (shift out)ȴ. bit ¸ check ִ. carry ־ bit clear/set ִ.(SETC, CLRC)

(5) N (Negative flag) : ȣ ִ. negative̸ setǰ positive̸ clearȴ. ׷ 196 N bit ٸ CPUʹ ణ ٸ Ѵ. .

80H+80H=00H ; (-)+(-) ϸ (-) Ǿ ϴµ, (+) Ǿ. N flag (-) Ǿ Ѵٴ Ű set('1')ȴ.

44H+44H=88H ; (+)+(+) ϸ (+) Ǿ ϴµ, (-) Ǿ. N flag (+)̾ Ѵٴ Ű clear('0')ȴ.

(6) V (oVerflow flag) : overflow setȴ. ,

8bit -128~+127, 16bit -32768~+32767 setȴ.

, unsigned byte >255 (0FFH) , unsigned word >65535 (0FFFFH) , signed byte -128(80H)>>+127(7FH) , signed word -32768 (8000H)>>+32767(7FFFH) setȴ.

shift left ɿ shiftϴ operand ֻ bit ϸ set ȴ.

(7) VT (oVerflow Trap flag) : V flag setǸ V flag setȴ. VT flag Ư (CLRVT, JVT, JNVT)θ clear ų ִ. V flag ˻ϴ ͺ VT flag ˻ϴ ȿ̴.

(8) ST (STicky flag) : shift right ɿ '1' ó carry flag shift Ŀ shift ST flag shiftȴ. ST flag shift right Ŀ Ҽ ̼ Ѵ.




 

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