8051
AVR
EZLab
PIC
80C196KC
DSP
ARM
VHDL
ũθ콺
κ౸
Battle κ
κȸ
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Embeded Linux
HW/SW
RTOS
 
 


2. 196


I. 196

1. 196 Ư¡

20MHz operation

RALU

488 byte internal RAM

28 interrupt source, 16 interrupt vector

1.4us 16bit X 16bit multiplication (at 20MHz)

Power down mode, Idle mode

16bit watchdog timer

full duplex serial port

8bit/16bit external BUS width

Capture ִ 16bit up/down counter

8/10bit ADC with Sample/Hold

232 byte register file

Register-Register Architecture

PTS(Peripheral Transaction Server)

HOLD/HOLDA protocol

5 8bit I/O port

3 PWM output

16bit software timer

2. 196

(1) 196KC memory

196KC memory map .

 

external Memory/IO

FFFFH ~ 4000H


internal ROM/EP-ROM or external ROM

3FFFH ~ 2080H


reserved



8 interrupt vector table

203FH ~ 2030H


EP-ROM security key

202FH ~ 2020H


reserved



CCB(Chip Configuration Byte)

2018H


reserved



8 interrupt vector table

2013H ~ 2000H


port 3, 4

1FFFH

1FFEH

Address/Data BUS

external memory Ǵ IO

1FFDH ~ 0200H


internal data memory, register file(SP, RAM, SFR, external program code memory)

01FFH

~

0000H

80C196KC internal RAM & SFR

 

RAM Register file ˾ƺ.

RAM memory map

 

RAM

01FFH ~ 0100H

window ̿Ͽ data access

Register File

00FFH ~ 001AH

direct, indirect, index addressing ̿Ͽ data access

SP(Stack Pointer)

0019H ~ 0018H

Stack Pointer

SFR(Special Function Register)

0017H ~ 0000H

I/O ٸ ֺ

 

1) Register File

80196 Register File base Ͽ ϴ Register to Register Architecture Ǿִ. register file 232byte RAM(18H~0FFH) register , 196KC 256byte ߰ RAM ־ window ̿Ͽ ִ.

18H~0FFH register file̶ θµ, byte(8bit), word(16bit), long word(32bit) access ִ. register file RALU(Register/Arithmetic Logic Unit) ϹǷ 232 Accumulator ִ Ͱ ȿ . , Ư Accumulator ̿Ͽ ʿ䰡 Ƿ α׷ ϴ.

, RAM SFR window ̿Ͽ 0100H~01FFH 256byte RAM register file mapping Ѽ RALU ִ.

2) Stack Pointer

16bit Stack Pointer Ǵ κ̴. ڰ ʱ Ͽ Ѵ.

3) SFR(Special Function Registers) & window

196 IO ϱ Register̴.SFR ˾ƾ߸ controller IO ־ ִ.

196 window ̿Ͽ ٸ SFR ִ. Ʒ ǥ 196 SFR̴.

 

address

window 0

Read

window 0

Write

window 1

Read/Write

window 15

Read

window 15

Write

17H

IOS2

PWMO_CONTROL

PWM2_CONTROL

PWM0_CONTROL

IOS2

16H

IOS1

IOC1

PWM1_CONTROL

IOC1

IOS1

15H

IOS0

IOC0

reserved

IOC0

IOS0

14H

WSR

WSR

WSR

WSR

WSR

13H

INT_MASK1

INT_MASK1

INT_MASK1

INT_MASK1

INT_MASK1

12H

INT_PEND1

INT_PEND1

INT_PEND1

INT_PEND1

INT_PEND1

11H

SP_STAT

SP_CON

reserved

SP_CON

SP_STAT

10H

PORT2

PORT2

reserved

reserved

reserved

0FH

PORT1

PORT1

reserved

reserved

reserved

0EH

PORT0

BAUD_RATE

reserved

reserved

reserved

0DH

TIMER2(HI)

TIMER2(HI)

reserved

T2CAPTURE(HI)

T2CAPTURE(HI)

0CH

TIMER2(LO)

TIMER1(LO)

IOC3

T2CAPTURE(LO)

T2CAPTURE(LO)

0BH

TIMER1(HI)

IOC2

reserved

IOC2

TIMER1(HI)

0AH

TIMER1(LO)

WATCHDOG

reserved

WATCHDOG

TIMER1(LO)

09H

INT_PEND

INT_PEND

INT_PEND

INT_PEND

INT_PEND

08H

INT_MASK

INT_MASK

INT_MASK

INT_MASK

INT_MASK

07H

SBUF(Rx)

SBUF(Tx)

PTSSRV(HI)

SBUF(Tx)

SBUF(Rx)

06H

HSI_STATUS

HSO_COMMAND

PTSSRV(LO)

HSO_COMMAND

HSI_STATUS

05H

HSI_TIME(HI)

HSO_TIME(HI)

PTSSEL(HI)

HSO_TIME(HI)

HSI_TIME(HI)

04H

HSI_TIME(LO)

HSO_TIME(LO)

PTSSEL(LO)

HSO_TIME(LO)

HSI_TIME(LO)

03H

AD_RESULT(HI)

HSI_MODE

AD_TIME

HSI_MODE

AD_RESULT(HI)

02H

AD_RESULT(LO)

AD_COMMAND

reserved

AD_COMMAND

AD_RESULT(LO)

01H

ZERO_REG(HI)

ZERO_REG(HI)

ZERO_REG(HI)

ZERO_REG(HI)

ZERO_REG(HI)

00H

ZERO_REG(LO)

ZERO_REG(LO)

ZERO_REG(LO)

ZERO_REG(LO)

ZERO_REG(LO)

 

* WSR (Window Select Register) ̿ؼ window ϴ

 

7

6

5

4

3

2

1

0

function

X

0

0

0

0

0

0

0

window 0

X

0

0

0

0

0

0

1

window 1

X

0

0

0

1

1

1

1

window 15

 

SFR address ٸ Register mapping Ǿ ִµ, ̴ 96 迭 controller ȣȯ ߰Ǹ鼭 ߻ ̴. Ư register ϱ ؼ WSR ̿Ͽ window ϰ register accessϴ ̴. а 󼭵 accessǴ address ޶Ƿ ؾ Ѵ. ̴ ڿ ſ ߿ϴ. ĩϸ Ǽ ã ̴.

(2) RALU

register CPU ؼ memoryκ Accumulator data ; Ѵ. ׷ 196 RAM(register) ׷ ʿ䰡 . , register accumulator Ѵ.

ϴ CPU

MOV AX, 40H

MOV BX, 50H

ADD AX, BX

MOV 40H, AX

ؾ, 196KC

ADD 40H, 50H

ٷ ȴ. (40H 50H )

196 , , ɿ operand ֱ , 60H=40H-50H(40H 50H 60H Ѵ.)

SUB 60H, 40H, 50H

ٿ ִ. ӵ ٸ CPU ӵ memory ȿ 10~30% ִ.

II. 196 Assember

II-I. Assembler ϱ

1. Assembler

⺻ mnemonic + operand ȴ. .

START: ADD AX, #40H

label mnemonic operands (AX variable)

mnemonic̶ ϴ ̰, operand ȴ. ̷ Assembler ؼ OP code ȯǾ object file . ̴ ٽ ROM̳ RAM ִ code() ȯǾ ǰ ȴ.

operand mnemonic ޶. ͵ ְ, ͵ ְ, ͵ ִ. ̵ CPU ٸ. ׷ ϱ ˰ ִٸ ٸ ׸ ʴ.

Programming Assembler ݵ . C ǰ C++ . ׷ Hardware ϱ ؼ Assembler ʼ̰, ̸ ˾ƾ߸ hardware ȿ ְ, code ִ. ׷Ƿ ӵ hardware Cٴ assembler ̴.

CPU assembler ִ. κ ϳ ణ ٸ Ƿ ڽ  assembler ϴ ˰ ؾ Ѵ. 8x86迭̶ MASM(Macro Assembler) ̴.

ĺʹ intel ϴ asm96 ̿Ͽ α׷ ߰ 캸ڴ. (196 assembler http://www.postech.ac.kr/downarea/asm/ic96.zip ٶ.) Ʒ ׸ program ̴. source program ؼ ̴ Assembleȴ. ⼭ list file ִ. ⿡ object file oh hex2bin ؼ hex file̳ bin file code .

                                        

2. 196 Assembler

켱 Ϲ ׵鿡 ؼ .

(1) ̸(Label, varible,...) ִ

ASCII ڴ ϰ, ҹ . ׷ ̸ ù ° ڷδ 0~9 ڸ ڴ . ̴ ִ 31̴.

(2) ǥ

 

߰

example

2 (binary)

B (b)

11000011B

8 (oxta)

O, Q (o, q)

145O

10 (decimal)

D, d Ȥ

95

16 (hexa)

H, h

9FH, 0F0H

 

16 lable̳ ̸ ڸ ϱ ؼ ó A~F ϴ 쿡 տ 0 ϳ ش.

(3)

Ͱ .

LOOP: ORB TEMP, #'A' ; Temp 'A' ASCII

lable mnemoic operands comment

(4) Lable, Variable, Number

1) Lable

Lable jump call subroutime Ȥ address ̸̸ ó ڿ ':' δ. ׷ assembler lable .

2) Variable

ġ Ÿ Ѵ.

) TEMP: DCB 155

TEMP1: DSB 15

(C - int temp;)

3) Number

ڷμ EQU(Equate) SET Ͽ ϰ .

) RADIUS EQU 450

(C define )

(5) Asm96 þ

 

þ

function

example

Module level ϴ þ

MODULE

module

ABC MODULE STACKSIZE(100)

PUBLIC

public symbol

ACC

EXTRN

ܺ symbol

ACD

END

end of program

END

Location counter ϴ þ

CSEG

code segment

CSEG AT 2080H

DSEG

data segment

DSEG AT 8000H

RSEG

overay ʴ register segment

RSEG AT 0020H

OSEG

overayǴ register segment

OSEG AT 0100H

ORG

address (Origin)

ORG 8200H

Symbol ϴ þ

EQU

symbol (ǰ Ұ)(Equate)

ESC EQU 0

SET

symbol (ǰ )

BEEP SET 0

Code ϴ þ

DCB

byte (Define Code in Byte)

DCB 33H, 'HI'

DCW

word (Define Code in Word)

DCW 4444H

DCL

long word (Define Code in Long word)

DCL 12345678H

DCR

Ǽ (Define Code in real)

DCR 3.14159

þ

IF


ELSE0

ü


ENDIF


 

196 (mnemonic) ɿ ɱ ִ. ̿ .

shift

branch

Stack subroutine system

Bit, Byte, Word, Long word ɵ ޶Ƿ ؾ Ѵ.

ðʹ .

̴ о ͵ Ͽ мغ.

( )

north equ 40h ;

west equ 0

east equ 80h

south equ 0c0h

CSEG AT 8004H ; AD interrupt

ljmp AD_SERVICE

CSEG AT 800CH ; HSO interrupt

ljmp HSO_SERVICE

CSEG AT 8014H ; Software timer interrupt

ljmp SOFT_TIMER

;CSEG AT 801CH ; extint

; LJMP EXTI_SERVICE

CSEG AT 8030H ; Timer2 overflow interrupt

ljmp timer2_service

CSEG AT 8200H

START: LDB IOC0, #00000000B ; all hsi unit is disable, select P2.3, P2.5

LDB IOC1, #01111010B ; HSO4, HSO5 enable, select ACH7 as exint1 input,

; timer2 overflow interrupt enable

LDB IOC2, #10010100B ; Fast mode AD enable, timer2 normal increasing mode

LDB WSR, #1

LDB IOC3, #000000001B ; timer2 clock source internal

CLRB WSR

CLRB IOPORT1 ; port initialize

CLRB IOPORT2

ldb ax, #0ffh ; ʱȭ

clrb ch

clrdl: stb ch, data_location[ax]

djnzw ax, clrdl

EI

restart: ldb current_dir, #north ; set direction (forward, absolute)

ldb current_xy, #0 ; set current coordinate (x, y = 0, 0)

ldb target_xy, #44h ; set destination

(ʻ)



 

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