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1. Controller°¡ ¹¹ÁÒ?

2. Memory¿Í IO

(1) Memory, IO ¶õ?

Memory¶õ ´Ü½Ã°£ ¶Ç´Â Àå½Ã°£ ±â¾ïÇÒ ¼ö ÀÖ´Â ¼ÒÀÚ¸¦ ¸»Çϴµ¥, Å©°Ô ROM°ú RAMÀ¸·Î ³ª´¶´Ù. RAMÀº Random Access Memory¸¦ ¸»Çϴµ¥, Èֹ߼ºÀ» °¡Áö°í À־ Àü¿øÀÌ ²¨Áö¸é ³»¿ëÀÌ ¾ø¾îÁø´Ù´Â °ÍÀ» Àß ¾Ë °ÍÀÌ´Ù. ÀÌ RAMÀº Å©°Ô SRAM(Static RAM)°ú DRAM(Dynamic RAM)ÀÇ µÎ °¡Áö·Î ºÐ·ùµÇ´Âµ¥, ¿ì¸®´Â ControlÀÌ ½¬¿î SRAMºÎÅÍ ´Ù·ç°Ô µÉ °ÍÀÌ´Ù. ¶Ç ROMÀº ±â´É¿¡ µû¶ó ¿©·¯ °¡Áö°¡ ÀÖ´Ù. ÈçÈ÷ Á¢ÇÒ ¼ö ÀÖ´Â °ÍÀ¸·Î´Â PROM(Programmable ROM, Çѹø¸¸ ¾µ ¼ö ÀÖ´Ù.), EPROM(Erasable PRAM, Áö¿ì°í ´Ù½Ã ¾µ ¼ö ÀÖ´Ù.)ÀÌ Àִµ¥, EPROM¿¡´Â UVEPROM(Ultraviolet, Àڿܼ±À¸·Î Áö¿ï ¼ö ÀÖ´Â EPROM)°ú EEPROM(Electrically EPROM)°ú Flash ROMÀÌ ÀÖ´Ù. EEPROM°ú Flash ROMÀº ¸ðµÎ Àü±âÀûÀ¸·Î Áö¿ï ¼ö°¡ ÀÖÁö¸¸, EEPROMÀº ¸Þ¸ð¸® cellÇÑ °³ ´ÜÀ§·Î Áö¿ì°í ¾µ ¼ö°¡ ÀÖÀ¸³ª Flash ROMÀº block´ÜÀ§ÀÇ »èÁ¦ ¹× ¾²±â°¡ °¡´ÉÇÏ´Ù´Â °ÍÀÌ ´Ù¸£´Ù. °ªÀº EEPROMÀÌ Flash ROMº¸´Ù ºñ½Î´Ù. º¸Åë ÈÞ´ë¿ë MP3 player¿¡´Â °ª ½Ñ Flash ROMÀÌ »ç¿ëµÈ´Ù. ¶Ç ¿äÁòÀÇ main board´Â BIOS°¡ Flash³ª EEPROMÀ¸·Î µÇ¾î À־ »ç¿ë»ç°¡ ³ôÀº versionÀÇ BIOS·Î ´Ù½Ã programmingÇÒ ¼ö ÀÖµµ·Ï µÇ¾îÀÖ´Ù.

IO´Â À§ÀÇ Memory¿Í °ÅÀÇ ºñ½ÁÇÑ ¼º°ÝÀ» °¡Áö°í ÀÖ´Ù. »ç½Ç Memoryµµ ÀÏÁ¾ÀÇ IO¶ó°í ÇÒ ¼ö ÀÖ´Ù. ±×·¯³ª ±× ±â´ÉÀÌ dataÀÇ ±â¾ïÀå¼Ò³ª ÇÁ·Î±×·¥ÀÇ À§Ä¡·Î »ç¿ëµÈ´Ù´Â Á¡ÀÌ ´Ù¸¥ °ÍÀÌ´Ù. º¸Åë PC¿¡¼­ ¸»ÇÏ´Â IO´Â ºñµð¿À Ä«µå, »ç¿îµå Ä«µå³ª ȤÀº °¢Á¾ port, keyboard, mouse µîÀÇ ÀÔ/Ãâ·Â ÀåÄ¡°¡ µÉ °ÍÀÌ´Ù. ÀÌµé ¿ª½Ã memory¿Í ¸¶Âù°¡Áö·Î ƯÁ¤ÇÑ address¿Í IRQ, DMA°¡ ÇÒ´çµÇ¾î ÀÖ´Ù. mouse³ª soccer robot¿¡¼­´Â motor³ª sensor°¡ IO¿¡ ÇØ´çÇÒ °ÍÀÌ´Ù.

(2) CPUÀÇ memory °ü¸®

System¿¡¼­ memory´Â ƯÁ¤ÇÑ address·Î ÇÒ´çµÇ¾î ÀÖ°Ô µÈ´Ù. ÀÌ´Â CPU°¡ memory¸¦ °ü¸®Çϱâ À§ÇÑ ¹æ¹ýÀÌ´Ù. Çϳª ÇϳªÀÇ memory cellÀº °¢°¢ÀÇ address¸¦ °¡Áö°í ÀÖ´Ù. CPU´Â À̸¦ access(Read or Write)Çϱâ À§Çؼ­ address BUS¿¡ ±× ÁÖ¼Ò¸¦ ³»º¸³»°í data BUS¸¦ ÅëÇؼ­ data¸¦ Àаųª ¾µ ¼ö°¡ ÀÖ´Ù. IO ¿ª½Ã memory¿Í ¸¶Âù°¡Áö·Î °¢°¢ÀÇ address¸¦ ÇÒ´ç¹Þ°Ô µÈ´Ù. ÀÌ¿Í °°Àº ¹æ¹ý¿¡¼­´Â CPU°¡ °ü¸®ÇÒ ¼ö ÀÖ´Â memoryÀÇ ¾çÀÌ Á¦ÇѵǾî Àִµ¥, ÀÌ´Â address BUSÀÇ Æø¿¡ µû¶ó °áÁ¤µÈ´Ù. ¿¹¸¦ µé¾î 16bit address bus¸¦ °¡Áø CPU´Â 2=64k °³ÀÇ memory ¿µ¿ªÀ» °¡Áú ¼ö ÀÖ´Ù. ¸¸¾à ÀÌ CPU°¡ ±âº»ÀûÀ¸·Î 8bit data BUS¸¦ °¡Áø´Ù¸é, ÃÑ 64kbyteÀÇ memory¸¦ °ü¸®ÇÒ ¼ö ÀÖ´Ù.

¶Ç memory¸¦ °ü¸®ÇÏ´Â ¹æ¹ý¿¡´Â segment address¸¦ »ç¿ëÇÏ´Â ¹æ¹ýÀÌ ÀÖ´Ù. Áï, ¸Þ¸ð¸®¸¦ ÀÛÀº ºÎºÐÀ¸·Î ´Ù½Ã ³ª´©¾î ¾²´Â ¹æ¹ýÀÌ´Ù. ÀÌ °æ¿ì ´ÙÀ½°ú °°ÀÌ address¸¦ Ç¥ÇöÇÑ´Ù.

0040:0FF4 0040Àº segment, 0FF4´Â offset

CPU´Â ÀÌ µÑÀ» ÀÌ¿ëÇØ ½ÇÁ¦ÀûÀÎ address¸¦ ¸¸µé¾î ³½´Ù. ÀÌ·± ¹æ½ÄÀ» segmented addressing À̶ó°í ÇÏ°í, ±×³É ½ÇÁ¦ ÁÖ¼Ò¸¦ »ç¿ëÇÏ´Â °æ¿ì¸¦ liniear addressingÀ̶ó°í ÇÑ´Ù. x86°è¿­Àº segmented addressingÀ» »ç¿ëÇÑ´Ù. ±×·¯³ª ´ëºÎºÐÀÇ controllerµéÀº »ç¿ëÇÒ ¼ö ÀÖ´Â memeoryÇÑ Å©Áö ¾ÊÀ¸¹Ç·Î linear addressingÀ» ¸¹ÀÌ »ç¿ëÇÑ´Ù.

(3) Address mapping, decoding

À§¿¡¼­ ¼³¸íÇÑ °Íó·³ ƯÁ¤ ¿µ¿ª¿¡ memory³ª IO¸¦ ÇÒ´çÇÏ´Â °ÍÀ» memory mapping, IO mapping ȤÀº ¸ðµÎ¸¦ address mappingÀ̶ó°í ÇÑ´Ù. ¶Ç CPU¿¡ µû¶ó¼­ memory¿Í IO¸¦ ±¸ºÐÇÏ¿© »ç¿ëÇÏ´Â °ÍÀÌ ÀÖ°í, memory¿Í IOÀÇ ±¸ºÐÀÌ ¾ø´Â °æ¿ì°¡ Àִµ¥, ÀüÀÚÀÇ °æ¿ì¸¦ memory mapped IO, ÈÄÀÚÀÇ °æ¿ì¸¦ IO mapped IO ¹æ½ÄÀ̶ó°í Çϴµ¥, ÀÌ °æ¿ì´Â memory¿Í IOÀÇ ¿µ¿ªÀÌ µ¶¸³µÇ¾î ÀÖ°Ô µÈ´Ù. ´ÙÀ½ ±×¸²Àº ÀÌ µÎ ¹æ½ÄÀÇ address mapÀ» ³ªÅ¸³½ °ÍÀÌ´Ù.

                                

                      ±×¸²1 memory mapped IO¿Í IO mapped IOÀÇ address space

3 bus architecture system¿¡¼­ memory³ª IO¿¡ Á¢±ÙÇϱâ À§Çؼ­´Â ÀÌ¿¡ ÇÊ¿äÇÑ control signalÀÌ ÇÊ¿äÇѵ¥, º¸Åë RD#, WR# ½ÅÈ£°¡ ÀÖ´Ù. RD#Àº low active signal·Î data¸¦ Àбâ À§ÇÑ ½ÅÈ£ÀÌ°í, WR#´Â low active signal·Î data¸¦ ¾²±â À§ÇÑ ½ÅÈ£ÀÌ´Ù. memory mapped IO¿¡¼­´Â MRD#, MWR#, IOR#, IOW# ȤÀº RD#, WR#, IO/MÀÇ ½ÅÈ£°¡ ÇÊ¿äÇÏ´Ù.

                                 

                                            ±×¸² 2 µÎ °æ¿ìÀÇ control signal

 ÇÑÆí memory¸¦ »ç¿ëÇÔ¿¡ À־ ƯÁ¤ ¿µ¿ªÀ» ƯÁ¤ ¿ëµµ·Î »ç¿ëÇϵµ·Ï mappingÀ» ÇÏ°Ô µÇ´Âµ¥, ÀÌ °úÁ¤À» address decodingÀ̶ó°í ÇÑ´Ù. ¶Ç ÀÌ·¸°Ô decoding ȤÀº mappingµÈ °¢ ¿µ¿ªÀ» ³ªÅ¸³½ °ÍÀ» address ȤÀº IO mapÀ̶ó°í ÇÑ´Ù. ¿¹¸¦ µé¾î PC(AT)ÀÇ address map°ú IO mapÀº ´ÙÀ½°ú °°´Ù.

interrupt vector table

0



BIOS data ¿µ¿ª

1K



MS-DOS program

device driver





Application program





ROM ¿µ¿ª

(ROM BIOS, video, etc)

640K


1M

 

DMA controller(8237A-5)

000-01F

Interrupt controller(8259A)

020-03F

Timer

040-05F

Keyboard(8042)

060-06F

Realtime clock(MC146818)

070-07F

DMA page resister

080-09F

Interrupt controller2(8259A)

0A0-0BF

DMA controller2(8237A-5)

0C0-0DF

Math Coprocessor

0F0-0F1

Math Coprocessor

0F8-0FF

Hard disk controller

1F0-1F8

Game port

200-207

Interface for 2nd parallel printer

278-27F

2nd serial interface

2F8-2FF

Prototype card

300-31F

Network card

360-36F

Interface for 1st parallel printer

378-37F

Monochrome Display Adapter

and parallel printer connection

3B0-3BF

Color/Graphics Adapter

3D0-3DF

Disk controller

3F0-3F7

1st serial interface

3F8-3FF

16 bit adderss BUS(A0~A15)ÀÇ °æ¿ì address decodingÀÇ ¿¹¸¦ µé¾îº¸¸é ´ÙÀ½°ú °°´Ù.

¿ì¸®°¡ ¿øÇÏ´Â memory mapÀº ´ÙÀ½°ú °°´Ù.

¿ëµµ

address(HEX)

address (Bin)

size

ROM

0000-7FFF

0000 0000 0000 0000 - 0111 1111 1111 1111

32k

RAM1

8000-BFFF

1000 0000 0000 0000 - 1011 1111 1111 1111

16k

RAM2

C000-DFFF

1100 0000 0000 0000 - 1101 1111 1111 1111

8k

IO

E000-FFFF

1110 0000 0000 0000 - 1111 1111 1111 1111

8k

¿©±â¼­ binary·Î Ç¥ÇöµÈ address¸¦ º¸¸é, »óÀ§ 3bitÀ¸·Î address¸¦ decoding ÇÒ ¼ö ÀÖÀ½À» ¾Ë ¼ö ÀÖ´Ù.

µû¶ó¼­ ¿©±â¿¡¼­ °¢°¢ÀÇ select ½ÅÈ£´Â ´ÙÀ½ ½Ä¿¡ ÀÇÇؼ­ ¸¸µé¾îÁú ¼ö ÀÖ´Ù.

ROM#    = A15

RAM1#   = A15' + A14

RAM2#   = A15' + A14' + A13

IO#     = A15' + A16' + A17'

¶Ç À̸¦ °£´ÜÈ÷ ±¸ÇöÇغ¸¸é ´ÙÀ½°ú °°´Ù.

                                

                                              ±×¸² 3 Address decoder

Âü°í> 74138ÀÇ Truth table

 

A

B

C

G1

G2

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

X

X

X

L

X

H

H

H

H

H

H

H

H

X

X

X

X

H

H

H

H

H

H

H

H

H

L

L

L

H

L

L

H

H

H

H

H

H

H

L

L

H

H

L

H

L

H

H

H

H

H

H

L

H

L

H

L

H

H

L

H

H

H

H

H

L

H

H

H

L

H

H

H

L

H

H

H

H

H

L

L

H

L

H

H

H

H

L

H

H

H

H

L

H

H

L

H

H

H

H

H

L

H

H

H

H

L

H

L

H

H

H

H

H

H

L

H

H

H

H

H

L

H

H

H

H

H

H

H

L


(4) Address / Data Bus Multiplexing, non-DMA cycle System BUS timing

CPU°¡ ¿ÜºÎ memory¸¦ accessÇϱâ À§Çؼ­´Â ¿ì¼± Address BUS¿Í Data BUS°¡ ÇÊ¿äÇÏ´Ù. ±×·±µ¥ CPU°¡ °ü¸®ÇÒ ¼ö ÀÖ´Â memory°¡ Ä¿Áö¸é address BUS Æøµµ ´Ã¾î³¯ °ÍÀÌ´Ù. ÀÌ·± ÀÌÀ¯·Î ¸¹Àº controllerµéÀº(intel °è¿­) Address BUS¿Í Data BUS°¡ multiplexµÇ¾î ÀÖ´Ù. 196ÀÇ °æ¿ì, 196Àº 16 bit data¸¦ »ç¿ëÇϹǷÎ, Address BUS 16bit¿Í Data BUS 16bit°¡ ÇÊ¿äÇϹǷÎ, ¿©±â¿¡ ÃÑ 32 °³ÀÇ ¿ÜºÎ pinÀÌ ÀÖ¾î¾ßÇÑ´Ù. µû¶ó¼­ chipÀÇ Å©±â°¡ Ä¿Áö¹Ç·Î, À̸¦ multiplexÇÏ¿© 16bit¸¸À» »ç¿ëÇÏ°í, ½Ã°£À» ºÐÇÒÇÏ°í Ưº°ÇÑ ½ÅÈ£¸¦ ¸¸µé¾î¼­ Address¿Í Data¸¦ ±¸º°Çϵµ·Ï ÇÑ´Ù. ÀÌ·¸°Ô Çϸé chipÀÇ Å©±â¸¦ ÁÙÀÏ ¼ö°¡ ÀÖ´Ù. º¸Åë ÀÌ·± CPU¿¡¼­´Â ALE(Address Latch Enable)À̶ó´Â ½ÅÈ£¸¦ µû·Î µÎ¾î¼­ ALE=1À̸é Address Ãâ·Â, ALE=0À̸é Data ÀÔÃâ·ÂÀ» ÇÏ°Ô µÈ´Ù. (°°Àº BUS¸¦ »ç¿ëÇÏ¿©) ÀÌ ¶§¹®¿¡, ÀÌ·¯ÇÑ CPU¿¡´Â ¿ÜºÎ¿¡ º°µµÀÇ Address Latch°¡ ÇÊ¿äÇÏ´Ù. Address¸¦ HoldingÇÏ°í ÀÖ¾î¾ß Çϱ⠶§¹®ÀÌ´Ù. (Address, Data ºÐ¸®) ´ÙÀ½Àº ÀÌ °æ¿ìÀÇ BUS±¸Á¶¿Í Latch »ç¿ëÀÇ ¿¹ÀÌ´Ù.

                                 

                                    ±×¸² 4 Address/ data BUSÀÇ multiplexing

¶Ç ÀÌ ¶§ÀÇ Read/Write timingÀº ´ÙÀ½°ú °°´Ù. (non DMA cycle)

                                

                                                      ±×¸² 5 Read Cycle

                                

                                                      ±×¸² 6 Write cycle



 

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