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1. Controller ?

2. Memory IO

(1) Memory, IO ?

Memory ܽð Ǵ ð ִ ڸ ϴµ, ũ ROM RAM . RAM Random Access Memory ϴµ, ֹ߼ ־ ٴ ̴. RAM ũ SRAM(Static RAM) DRAM(Dynamic RAM) зǴµ, Control SRAM ٷ ̴. ROM ɿ ִ. ִ δ PROM(Programmable ROM, ѹ ִ.), EPROM(Erasable PRAM, ٽ ִ.) ִµ, EPROM UVEPROM(Ultraviolet, ڿܼ ִ EPROM) EEPROM(Electrically EPROM) Flash ROM ִ. EEPROM Flash ROM , EEPROM ޸ cell Flash ROM block ϴٴ ٸ. EEPROM Flash ROM δ. ޴ MP3 player Flash ROM ȴ. main board BIOS Flash EEPROM Ǿ ־ version BIOS ٽ programming ֵ Ǿִ.

IO Memory ִ. Memory IO ִ. ׷ data ҳ α׷ ġ ȴٴ ٸ ̴. PC ϴ IO ī, ī峪 Ȥ port, keyboard, mouse / ġ ̴. ̵ memory Ư address IRQ, DMA ҴǾ ִ. mouse soccer robot motor sensor IO ش ̴.

(2) CPU memory

System memory Ư address ҴǾ ְ ȴ. ̴ CPU memory ϱ ̴. ϳ ϳ memory cell address ִ. CPU ̸ access(Read or Write)ϱ ؼ address BUS ּҸ data BUS ؼ data аų ִ. IO memory address Ҵް ȴ. ̿ CPU ִ memory ѵǾ ִµ, ̴ address BUS ȴ. 16bit address bus CPU 2=64k memory ִ. CPU ⺻ 8bit data BUS ٸ, 64kbyte memory ִ.

memory ϴ segment address ϴ ִ. , ޸𸮸 κ ٽ ̴. address ǥѴ.

0040:0FF4 0040 segment, 0FF4 offset

CPU ̿ address . ̷ segmented addressing ̶ ϰ, ׳ ּҸ ϴ liniear addressing̶ Ѵ. x86迭 segmented addressing Ѵ. ׷ κ controller ִ memeory ũ Ƿ linear addressing Ѵ.

(3) Address mapping, decoding

ó Ư memory IO Ҵϴ memory mapping, IO mapping Ȥ θ address mapping̶ Ѵ. CPU memory IO Ͽ ϴ ְ, memory IO 찡 ִµ, memory mapped IO, 츦 IO mapped IO ̶ ϴµ, memory IO Ǿ ְ ȴ. ׸ address map Ÿ ̴.

                                

                      ׸1 memory mapped IO IO mapped IO address space

3 bus architecture system memory IO ϱ ؼ ̿ ʿ control signal ʿѵ, RD#, WR# ȣ ִ. RD# low active signal data б ȣ̰, WR# low active signal data ȣ̴. memory mapped IO MRD#, MWR#, IOR#, IOW# Ȥ RD#, WR#, IO/M ȣ ʿϴ.

                                 

                                            ׸ 2 control signal

  memory Կ ־ Ư Ư 뵵 ϵ mapping ϰ Ǵµ, address decoding̶ Ѵ. ̷ decoding Ȥ mapping Ÿ address Ȥ IO map̶ Ѵ. PC(AT) address map IO map .

interrupt vector table

0



BIOS data

1K



MS-DOS program

device driver





Application program





ROM

(ROM BIOS, video, etc)

640K


1M

 

DMA controller(8237A-5)

000-01F

Interrupt controller(8259A)

020-03F

Timer

040-05F

Keyboard(8042)

060-06F

Realtime clock(MC146818)

070-07F

DMA page resister

080-09F

Interrupt controller2(8259A)

0A0-0BF

DMA controller2(8237A-5)

0C0-0DF

Math Coprocessor

0F0-0F1

Math Coprocessor

0F8-0FF

Hard disk controller

1F0-1F8

Game port

200-207

Interface for 2nd parallel printer

278-27F

2nd serial interface

2F8-2FF

Prototype card

300-31F

Network card

360-36F

Interface for 1st parallel printer

378-37F

Monochrome Display Adapter

and parallel printer connection

3B0-3BF

Color/Graphics Adapter

3D0-3DF

Disk controller

3F0-3F7

1st serial interface

3F8-3FF

16 bit adderss BUS(A0~A15) address decoding  .

츮 ϴ memory map .

address(HEX)

address (Bin)

size

ROM

0000-7FFF

0000 0000 0000 0000 - 0111 1111 1111 1111

32k

RAM1

8000-BFFF

1000 0000 0000 0000 - 1011 1111 1111 1111

16k

RAM2

C000-DFFF

1100 0000 0000 0000 - 1101 1111 1111 1111

8k

IO

E000-FFFF

1110 0000 0000 0000 - 1111 1111 1111 1111

8k

⼭ binary ǥ address , 3bit address decoding ִ.

⿡ select ȣ Ŀ ؼ ִ.

ROM#    = A15

RAM1#   = A15' + A14

RAM2#   = A15' + A14' + A13

IO#     = A15' + A16' + A17'

̸ غ .

                                

                                              ׸ 3 Address decoder

> 74138 Truth table

 

A

B

C

G1

G2

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

X

X

X

L

X

H

H

H

H

H

H

H

H

X

X

X

X

H

H

H

H

H

H

H

H

H

L

L

L

H

L

L

H

H

H

H

H

H

H

L

L

H

H

L

H

L

H

H

H

H

H

H

L

H

L

H

L

H

H

L

H

H

H

H

H

L

H

H

H

L

H

H

H

L

H

H

H

H

H

L

L

H

L

H

H

H

H

L

H

H

H

H

L

H

H

L

H

H

H

H

H

L

H

H

H

H

L

H

L

H

H

H

H

H

H

L

H

H

H

H

H

L

H

H

H

H

H

H

H

L


(4) Address / Data Bus Multiplexing, non-DMA cycle System BUS timing

CPU ܺ memory accessϱ ؼ 켱 Address BUS Data BUS ʿϴ. ׷ CPU ִ memory Ŀ address BUS þ ̴. ̷ controller(intel 迭) Address BUS Data BUS multiplexǾ ִ. 196 , 196 16 bit data ϹǷ, Address BUS 16bit Data BUS 16bit ʿϹǷ, ⿡ 32 ܺ pin ־Ѵ. chip ũⰡ ĿǷ, ̸ multiplexϿ 16bit ϰ, ð ϰ Ư ȣ  Address Data ϵ Ѵ. ̷ ϸ chip ũ⸦ ִ. ̷ CPU ALE(Address Latch Enable)̶ ȣ ξ ALE=1̸ Address , ALE=0̸ Data ϰ ȴ. ( BUS Ͽ) , ̷ CPU ܺο Address Latch ʿϴ. Address Holdingϰ ־ ϱ ̴. (Address, Data и) BUS Latch ̴.

                                 

                                    ׸ 4 Address/ data BUS multiplexing

Read/Write timing . (non DMA cycle)

                                

                                                      ׸ 5 Read Cycle

                                

                                                      ׸ 6 Write cycle



 

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