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2. 196

 

5. Interrupt

5-1. Interrupt?

interrupt ǹ̴ "ä"̴. interrupt processor óϴ ߿ Ư Է̳ ߻ Ư ǿ شϴ ϵ ϱ ؼ Ѵ. α׷ Ŀ interruptİ polling ִµ, polling̶,  event Ͼ⸦ ٸ ̴.  signal pollingϰ ٸ ۾ . processor ȿ . ׷ interrupt ϸ, ۾ ߿ Ư Է¿ ó Ƿ ξ ȿ ̴. C scanf() Ѵٸ, ̴ data polling ϴ ̹Ƿ, ̸ ϴ CPU ٸ . Է random ȣ óؾ ϴ , interrupt ϴ ȿ̴.

interrupt óϱ ؼ interrupt ȣ Ǿ° Ÿ interrupt pending register ʿϰ, interrupt source ϴ interrupt ϱ interrupt priority register, ׸ interrupt enable/disableϱ interrupt mask register ʿϴ. , controller interrupt Ƿ, register bit interrupt شϰ ̴. ׸ interrupt enable/disableϴ bit ְ ȴ. ̶, interrupt û  routine ΰ ʿѵ, ̰ ٷ IVT(Interrupt Vector Table)̴. ⿡ interrupt û б ּҰ ǰ, Vector ġ Ǿ ִ. бϴ ġ ISR(Interrupt Service Routine) Ͽ, routine interrupt · ư ȴ. PC PC setup IRQ settingϴ ̴. ̴ IRQ IO ΰ ִ ̴. 196 interrupt ؼ ˾ƺ.

5-2. 196KC Interrupt ó

5-2-1. Interrupt ó

196KC interrupt ó .

                                     

(1) up edge (transition detector) interrupt request(interrupt û ȣ 𼭸()) νؼ

(2) interrupt pending register interrupt source شϴ bit set Ų. , register ִ ٸ bit ̹ ٸ interrupt source interrupt ǥϱ Ͽ setǾ ִ.

(3) interrupt request CPU ޾Ƽ óϱ ؼ Ͽ Ѵ.

interrupt pending register ش bit setǾ־ Ѵ.

interrupt mask register شǴ bit setǾ־ Ѵ.

PSW ִ ü interrupt enable bit(global interrupt enable bit, PSW.9) set Ǿ ־ Ѵ.

(4) ϴ interrupt priority interrupt ϴ priority encoder ϰ ȴ. priority Ʒ ǥ hardware Ǿ ִ.

(5) interrupt Ʒ ǥ interrupt vector table Ҵ address address ISR address ־ Ѵ. (׷Ƿ, Table word ȴ.) ̷ ؼ ó routine branchؼ program ϰ ȴ. branch branch ޸ subroutine call (CALL) ̷Ƿ, ISR ݵ main program return ؾ Ѵ. (RET)

interrupt ȣ

interrupt source

IVT

priority

INT00

Timer overflow

2000H

0

INT01

AD conversion done

2002H

1

INT02

HSI data set

2004H

2

INT03

HSO

2006H

3

INT04

HSI.0 pin

2008H

4

INT05

software timer

200AH

5

INT06

serial I/O (TXD, RXD)

200CH

6

INT07

EXTINT (External interrupt)

200EH

7

Ư

TRAP instruction

2010H

-

Ư

unimplemented OP code

2012H

-

INT08

TI flag (TX)

2030H

8

INT09

RI flag (RX)

2032H

9

INT10

HSI FIFO 4

2034H

10

INT11

Timer 2 capture

2036H

11

INT12

Timer 2 overflow

2038H

12

INT13

EXTINT1

203AH

13

INT14

HSI FIFO FULL

203CH

14


PTS



INT15

NMI

203EH

15

 

5-2-2. Interrupt Source

interrupt ε鿡 ؼ ڼ ϸ .

                                   

׸ interrupt شǴ IO control register ̸ ؾ interrupt Ͼ ִٴ ̴. interrupt ߻ device ϸ鼭 ڼ ٷ絵 Ѵ. interrupt غ .

(1) INT00 : Timer1 Timer2 overflow interruptμ timer FFFFH 0000H Ǹ interrupt ߻Ѵ. IOC1 bit2 setŰ, timer1 ϸ, bit3 set Ű timer2 Ѵ. ׸ overflow checkϷ IOS1 bit4(timer2), bit5(timer1) checkϸ ȴ. timer2 interrupt source IOC2 bit5 "0" ϸ timer2 FFFFH0000H interrupt ߻ϰ, "1" ϸ, 7FFFH8000H interrupt ߻Ѵ.

(2) INT01 : ADC conversion ߻ϴ interrupt̴.

(3) INT02 : IOC1.7=1 HSI FIFO data loadǸ ߻ϴ interrupt̴. IOC1.7=0̸ holding register load interrupt ߻Ѵ.

(4) INT03 : interrupt HSO event Ͼ ߻ϴ interruptμ HSO.0~HSO.5 ؼ interrupt ִ. HSO_COMMAND register bit0~3 HSO pin ȣ bit4 interrupt enable/disable ִ. IOS2 ̿Ͽ HSO event check ִ.

(5) INT04 : interrupt HSI.0 pin up-edge ܺ interrupt ȴ. interrupt HSI FIFO enable ʿ .

(6) INT05 : software timer interruptμ software timer ÿ interrupt ߻ ִ. interrupt HSO_COMMAND bit0~3 software timerȣ bit4 "1" ϸ ȴ.

(7) INT06 : serial / interruptμ / interrupt̴.(۽ŵ ŵ interrupt ߻Ѵ.)

(8) INT07 : ܺ interruptμ ִ. IOC1.1=0̸ P2.2(EXTINT), IOC1.1=1̸ P0.7(EXTINT1) õȴ. Ȱ up-edge triggerȴ.

(9) INT08, INT09 : serial / interrupt INT08 ۽, INT09 interrupt INT06 ޸ /ſ ִ. interrupt INT06 disableŲ.

(10) INT10 : HSI FIFO ̻ data Էµ ߻ϴ interrupt̴.

(11) INT11 : P2.7(T2CAPTURE) up-edge ߻ϴ interrupt̸, timer2 T2CAPTURE register ȴ.

(12) INT12 : INT00 timer2 overflow interrupt̴.

(13) INT13 : ܺ interrupt P0.7 up-edge interrupt ߻Ѵ.

(14) INT14 : HSI FIFO full ߻ϴ interrupt̴.

5-3. Interrupt Control

5-3-1. Interrupt Pending Register

interrupt pending register ռ ó interrupt request Դ Ÿ register̴. 196KC INT_PEND, INT_PEND1 register ̴ Ѵ.

(1) interrupt source߿ 01 transition , PSW.9 IE bit Ǵ interrupt mask register Ʒ ׸ interrupt source Ǵ bit setȴ.

7

6

5

4

3

2

1

0

12H: INT_PEND1

13H: INT_MASK1

NMI

FIFO

full

EXTINT1

T2

overflow

T2

capture

HSI FIFO

full

RI

TI

 


7

6

5

4

3

2

1

0

09H: INT_PEND

08H: INT_MASK

EXTINT

serial

port

software

timer

HSI.0 pin

HSO pin

HSI data

A/D

done

timer

overflow

 

(2) interrupt vector pending register ش bit clearȴ.

(3) interrupt pending bit software setų ̸ ̿ϸ software interrupt request ִ.

(4) INT_PEND, INT_PEND1 interrupt ˻ϱ ؼ ִ.

5-3-2. Interrupt Mask Register

interrupt mask register interrupt mask register ش bit set, clear Ŵμ interrupt enable/disableų ִ register̴. 196KC INT_MASK, INT_MASK1 register ְ ̵ interrupt pending register ¸ . Ʒ ǥ interrupt source ʿ IO control register̴.

interrupt

mask

control bit

required register or bit

NMI

INT_MASK1.7

NMI pin


HSI FIFO full

INT_MASK1.6

IOC1.7=1

IOC0

EXTINT1 pin

INT_MASK1.5

IOC1.1


T2 overflow

INT_MASK1.4

IOC1.3=1, IOC2.5


T2 capture

INT_MASK1.3

P2.7()


HSI FIFO 4

INT_MASK1.2


IOC0

RI

INT_MASK1.1



TI

INT_MASK1.0


IOC1.5

EXTINT

INT_MASK.7

IOC1.1


serial port

INT_MASK.6


SP_CON, baud rate, IOC1.5=1

software timer

INT_MASK.5

HSO_COMMAND


HSI.0

INT_MASK.4

HSI pin()


HSO

INT_MASK.3

HSO_COMMAND


HSI data valid

INT_MASK.2

IOC1.7=0

IOC0

AD conversion done

INT_MASK.1


AD_Command, HSO_Command

timer overflow

INT_MASK.0

IOC1.2, IOC1.3=1


 

Interrupt mask register Ѵ.

(1) INT_MASK, INT_MASK1 byte registerμ read/write , شǴ bit setŰ interrupt enable, clearŰ interrupt disable ȴ.

(2) INT_MASK, INT_MASK1 bit clearǾ ִ interrupt request interrupt pending register ش bit setǹǷ, software interrupt request ˻ ִ.

(3) interrupt vector  interrupt pending register شǴ bit clear, interrupt mask register clear Ƿ software clearѾ Ѵ.

(4) INT_MASK1 ִ NMI bit ƹ . , NMI bit "0"̰, "1"̰ NMI(None Maskable Interrupt) enable/disableų .

(5) reset Ŀ interrupt mask register clearȴ. (interrupt disable)

(6) PUSHF/POPF INT_MASK, PSW stack ϰų , INT_MASK1 byte registeṟ WSR PUSHA/POPA ̿Ͽ ϰų ٽ ִ. PUSHF, PUSHA PSW interrupt mask register clearϱ ϰ interrupt disableȴ. ISR ISR ó ξ߸ routine ʴ´. ISR POPF/POPA Ͽ, interrupt mask register PSW, WSR ƾ Ѵ.

5-3-3. Interrupt ü enable

NMI, TRAP, unimplemented OP code interrupt interrupt PSW I bit(PSW.9) clearŰ disableǰ, PSW.9 setǰ, INT_MASK, INT_MASK1 ش bit setǾ enableȴ. 196 ̸ Ư ִ.

EI (Enable Interrupt) ; ü interrupt enable

DI (Disable Interrupt) ; ü interrupt disable

5-4. Ư Interrupt

5-4-1. NMI (None Maskable Interrupt)

NMI priority ´. Ī INT_MASK1 NMI bit , ǹ̰ . ȣȯ NMI bit 0 δ . NMI , ܺ NMI pin groundϸ ȴ.

5-4-2. TRAP

TRAP software interrupt Ȥ software debugger ϴ ־ single step ϰ ִ. TRAP interrupt Ѵ.

5-4-3. Unimplemented OP code

80C196KC ǵ OP code 쿡 ߻ϴ interrupt̴.

5-5. Interrupt Priority

priority encoder ̰ų enable interrupt߿ priority interrupt ISR ϰ Ѵ. ǥ ִ ó priority hardware ִ. ⼭ 15 priority̴. priority Ϸ software mask register Ͽ Ѵ.

serial(RX) interrupt routine ܺ interrupt ϰ ٸ interrupt ϸ ȴ.

interrupt vector table 2038H label SERIAL_RI_ISR Ǿ ־ϸ, routine ϱ Ͽ interrupt enableǾ ־ Ѵ.

CSEG AT 2038H

DCW SERIAL_RI_ISR

:: :: :: ::

CSEG AT 3000H

SERIAL_RI_ISR: PUSHA

LDB INT_MASK, #10000000B ; EXTINT enable

EI ; interrupt enable

:: ::

POPA

RET

ISR ϸ .

(1) ISR  ,

IP stack pushϰ,

̰ mask priority Ǵ vector IP loadѴ.

hardware interrupt call ٷ Ŀ ٸ interrupt ȴ´. ̰ interrupt call ۵Ǹ ISR ù ° ϱ ̴.

(2) PUSHA

stack PSW ϰ PSW clearŲ.

INT_MASK1 WSR stack pushϰ INT_MASK1 clearȴ. ̰ ISR INT_MASK1 WSR ְ ϱ ̴.

80C196KC PUSHA interrupt ʴ´. LDB interrupt enable flag clearǾ Ƿ LDB INT_MASK1,.... ϰ Ǵ ̴.

LDB INT_MASK1,.. SERIAL_RI_ISR interrupt service routine ٸ interrupt ϵ interrupt enable Ű ̴. EXTINT interrupt enable ״. EXTINT ƴ ٸ interrupt enableų ִ. INT_MASK1 register ̿Ͽ Ư interrupt enableŴμ hardware software interrupt priority ִ.

EI interrupt enable bit(PSW.9) setμ interrupt enable Ų. ISR software priority ȴ.

ISR POPA PSW interrupt mask register WSR ٽ ãƿ´. ISR interrupt mask register Ǿ POPA Ҿ ȴ. hardware POPA ɰ RETɱ interrupt request õȴ.

             : http://www.postech.ac.kr/group/poweron/ - lectures/Micro processor, controller, Ƹ

                               : Micro controller 80196 ʺ -



 

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