8051
AVR
EZLab
PIC
80C196KC
DSP
ARM
VHDL
ũθ콺
κ౸
Battle κ
κȸ
޸շκ
Embeded Linux
HW/SW
RTOS
 
 

 2. 196

 

4. 196KC IO port

 

4-1. 80C196KC SFR

տ ̹ SFR , ⿡ ٽ ϵ Ѵ.

IO port SFR ؼ Ѵ. port3 4 80C196KC ֺ ġ SFR ̿Ͽ ִ. SFR accessϴµ ־ window ؾ Ѵ. ٽ ǥ ϵ Ѵ. Ʒ ǥ κ 196KC IO port ϱ SFR̴.

address

window 0

Read

window 0

Write

window 1

Read/Write

window 15

Read

window 15

Write

17H

IOS2

PWMO_CONTROL

PWM2_CONTROL

PWM0_CONTROL

IOS2

16H

IOS1

IOC1

PWM1_CONTROL

IOC1

IOS1

15H

IOS0

IOC0

reserved**

IOC0

IOS0

14H

WSR

WSR

WSR

WSR

WSR

13H

INT_MASK1

INT_MASK1

INT_MASK1

INT_MASK1

INT_MASK1

12H

INT_PEND1

INT_PEND1

INT_PEND1

INT_PEND1

INT_PEND1

11H

SP_STAT

SP_CON

reserved**

SP_CON

SP_STAT

10H

PORT2

PORT2

reserved**

reserved**

reserved**

0FH

PORT1

PORT1

reserved**

reserved**

reserved**

0EH

PORT0

BAUD_RATE

reserved**

reserved**

reserved**

0DH

TIMER2(HI)

TIMER2(HI)

reserved**

T2CAPTURE(HI)

T2CAPTURE(HI)

0CH

TIMER2(LO)

TIMER1(LO)

IOC3

T2CAPTURE(LO)

T2CAPTURE(LO)

0BH

TIMER1(HI)

IOC2

reserved**

IOC2

TIMER1(HI)

0AH

TIMER1(LO)

WATCHDOG

reserved**

WATCHDOG

TIMER1(LO)

09H

INT_PEND

INT_PEND

INT_PEND

INT_PEND

INT_PEND

08H

INT_MASK

INT_MASK

INT_MASK

INT_MASK

INT_MASK

07H

SBUF(Rx)

SBUF(Tx)

PTSSRV(HI)

SBUF(Tx)

SBUF(Rx)

06H

HSI_STATUS

HSO_COMMAND

PTSSRV(LO)

HSO_COMMAND

HSI_STATUS

05H

HSI_TIME(HI)

HSO_TIME(HI)

PTSSEL(HI)

HSO_TIME(HI)

HSI_TIME(HI)

04H

HSI_TIME(LO)

HSO_TIME(LO)

PTSSEL(LO)

HSO_TIME(LO)

HSI_TIME(LO)

03H

AD_RESULT(HI)

HSI_MODE

AD_TIME

HSI_MODE

AD_RESULT(HI)

02H

AD_RESULT(LO)

AD_COMMAND

reserved**

AD_COMMAND

AD_RESULT(LO)

01H

ZERO_REG(HI)

ZERO_REG(HI)

ZERO_REG(HI)

ZERO_REG(HI)

ZERO_REG(HI)

00H

ZERO_REG(LO)

ZERO_REG(LO)

ZERO_REG(LO)

ZERO_REG(LO)

ZERO_REG(LO)

** reserved byte 0 .

.

ANDB IOS2, 50H

̴ IOS2 50H ANDϿ IOS2 ϱ α׷̴. ׷ ̴ ߸ ̴. IOS2 50H ϱ ؼ 50H IOS2 о ϴµ, ⿡ IOS2 аԵǸ( WSR=0̶ , default) IOS2 ǹǷ ̻ ̴. ׷ ̸ ٽ IOS2 Ǹ, ̶ IOS2 ƴ϶, PWM0_CONTROL ȴ. ġ ̴. α׷ ľ Ѵ.

LDB 40H, IOS2 ; 40H ӽ register

ANDB 40H, 50H

LDB WSR, #15 ; IOS2 ؼ window 15

LDB IOS2, 40H

CLRB WSR ; window

ռ ̹ , ߿ϱ ٽ Ѵ. δ SFR ̴.

196KC SFR ̴. SFR ɿ ó ǹǷ ⿡ SFR ɿ , ʹ device ʿ SFR ϰ ̴.

register

ZERO_REG

Zero register ׻ 0000H Ǿ ִ.

AD_RESULT

A/D ȯ A/D converter ° ȴ.

AD_COMMAND

A/D converter Ѵ.

HSI_MODE

HSI(High Speed Input) trigger pulse mode Ѵ.

HSI_TIME

HSI trigger timer1 ȴ.

HSO_COMMAND

HSO(High Speed Output) Ѵ.

HSI_STATUS

HSI pin ° ȴ.

SBUF(TX)

transmit buffer for serial port

SBUF(RX)

receive buffer for serial port

INT_MASK

interrupt mask register, ش bit 0/1 interrupt disable/enable

INT_PEND

interrupt ȣ Է ¸ ǥѴ.

WATCHDOG

64K state ð  CPU reset ɸ ð ȸѴ.

TIMER1

Timer1 Ѵ.

TIMER2

Timer2 Ѵ.

PORT0

port0 digital Է ȣ Ѵ.

BAUD_RATE

serial port / baud rate Ѵ.

PORT1

port1 / register

PORT2

port2 / register

SP_STAT

serial port status register

SP_CON

serial port control register

IOS0

IO status register 0

IOS1

IO status register 1

IOS2

IO status register 2

IOC0

IO control register 0

IOC1

IO control register 1

IOC2

IO control register 2

IOC3

IO control register 3

PWM_CONTROL

PWM(Pulse Width Modulation) counter. PWM pulth width Ѵ.

INT_PEND1

interrupt pending register 1 (196KC 8 interrupt)

INT_MASK1

interrupt mask register 1

WSR

Window Select Register

4-2. IO control register status register

 

IOC0   (15H HWIN 0 write)

          (15H HWIN 15 read)

0

HSI.0 input enable/

1

Timer2 reset each write

2

HSI.1 input enable/

3

Timer2 external reset each write

4

HSI.2 input enable/

5

Timer2 reset source HSI.0/

6

HSI.3 input enable/

7

Timer2 clock source HSI.1/

IOS0   (15H HWIN 0 read)

          (15H HWIN 15 write)

0

HSO.0

1

HSO.1

2

HSO.2

3

HSO.3

4

HSO.4

5

HSO.5

6

CAM or holding register full

7

HSO holding register full

IOC1    (16H HWIN 0 write)

        (16H HWIN 15 read)

0

select PWM/

1

external interrupt ACH7/

2

Timer1 overflow interrupt enable/

3

Timer2 overflow interrupt enable/

4

HSO.4 output enable/

5

select TXD/

6

HSO.5 output enable/

7

HSI interrupt

FIFO full/

IOS1 (16H HWIN 0 read)

(16H HWIN 15 write)

0

software TIMER0 expired

1

software TIMER1 expired

2

software TIMER2 expired

3

software TIMER3 expired

4

TIMER2 has overflow

5

TIMER1 has overflow

6

HSI FIFO is full

7

HSI holding register data available

bit 0-5 are cleared when read

IOC2 (0BH HWIN 0 write)

(0BH HWIN 15 read)

0

enbale fast increment of T2

1

enable T2 as up/down counter

2

enable/2 prescaler on PWM

3

enable 80C196KC A/D modes

4

A/D clock prescaler diable

5

T2 alternate interrupt 7FFFH->8000H

6

enable locked CAM enters

7

clear enter CAM*

* this bit always reads as 1

IOS2 (17H HWIN 0 read)

(17H HWIN 15 write)

indicated which HSO event occurred

0

HSO.0

1

HSO.1

2

HSO.2

3

HSO.3

4

HSO.4

5

HSO.5

6

T2RESET

7

start A/D

IOS2 is cleared when read

IOC3 (0CH HWIN 1 read/write)

0

Timer2 clock internal/

1

RSV*

2

PWM 1 enable/

3

PWM 2 enable/

4

RSV*

5

RSV*

6

RSV*

7

TSV*

RSV* bit must be writen as 0

4-3. Port

80C196KC P0, P1, P2, P3, P4 5 IO port , port 0, 1, 2 ϸ ̵ SFR ؼ Ѵ. port 1, 2 schmitt trigger Է° CMOS level ִ.

1. Port 0 (P0.0/ACH0 ~ P0.7/ACH7)

port0 Է port ̸, ditital Է ְ, ADC analog Է ִ. P0.7 ܺ interrupt request ȣ ִ.

digital Է 쿡 SFR PORT0(0EH) readϸ P0.0~P0.7 ִ.(byte) ̶ port 0 high-impedance Է ȴ.

ADC 쿡 analog Է ִ.

IOC1 bit1 "0" ϸ, P0.7 ܺ interrupt request pin ִ.

2. Port 1 (P1.0 ~ P1.7)

port1 Է/ , ⼺(quasi-bidirectional) port̴. 196KC P1.0~P1.2 ɸ , P1.3~P1.7 ٸ Ư pin ִ. port1 SFR PORT1(0FH) ؼ а ִ.

port number

direction

ٸ

P1.3

output

PWM1

P1.4

output

PWM2

P1.5

output

P1.6

output

P1.7

input

 

port, "L" ϰ, "H" ϴ port Ѵ. "H" ܺο "L" ߸ ִ.

port Է , port "0" ¿ Էϸ, port pin ´ "0" ϰ ֱ Է ȣ "0" readȴ. Է ϱ ݵ port "1" writeϰ о Ѵ.

3. Port 2 (P2.0 ~ P2.7)

port2 Է/ port , P2.6 P2.7 ִ. Ϲ port Ư ؼ ȴ. Ư ϱ ؼ شǴ SFR ش bit control ؾѴ. port2 SFR PORT2(10H) ؼ access ִ.

port number

direction

ٸ

P2.0

output

TXD

P2.1

input

RXD

P2.2

input

EXINT

P2.3

input

T2CLK

P2.4

input

T2RST

P2.6

input

T2_U/D

P2.7

input

T2_CAPTURE

 

4. Port 3, 4

port open drain / portμ, 196 memory mapped IO port Ѵ. , port0,. 1, 2 SFR ؼ access . port address/data bus DZ , Ϲ port ʴ´. port3 4 address 1FFEH, 1FFFH ҴǾ ִ.

            

           : http://www.postech.ac.kr/group/poweron/ - lectures/Micro processor, controller, Ƹ  

                            : Micro controller 80196 ʺ -


 

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