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80C196KC
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2. 196

 

II. 196 pin bus cycle, board design

II-I. 80C196KC  

1. VCC : main power(5V)

2. VSS : digital ground

3. VREF : Reference voltage for the ADC, +5V, ADC ޵Ǵ analog , port 0 logic readϴµ ǹǷ, port0 ADC Է ϴ, digital Է ϴ ݵ ؾ Ѵ.

4. ANGND : Analog ground, ADC analog ̴. VSS Ǿ Ѵ. , digital ground digital noise analog ground ʵ ؾ Ѵ. , analog GND digital GND point-to-point ϴ .

5. Vpp : peak to peak voltage,

power down ȸο returnϱ timing pin, 1uF capacitor Vss, 1M װ Vcc Ѵ.

87C196KC Ǿ ִ EP-ROM writeϴ Ѵ. ʴ´ٸ, Vcc Ѵ.

6. XTAL1 : clock ߻ oscillator inverter Է

7. XTAL2 : oscillator inverter . XTAL1 XTAL2 oscillator crystal Ͽ Ѵ. ̴ reference ȸθ ϸ ȴ.

 

 8. CLKOUT : Clock out, clock oscillator . oscillator frequency 1/2(duty 50%) frequency µȴ.

 9. : reset Է, open drain , active Low, ּ 16 state logic "L" ԷµǾ ϸ, reset sequence .

   clock up-edge clkout ٽ (synchronize)Ǿ, 10 state PSW clear,

   2018H byte о CCR(Chip Configuration Register) load

   2080H jumpؼ program Ѵ. CPU SFR ܺ pin Ư ʱȭǴµ, 80C196KC Reset status .

10. NMI(Non Maskable Interrupt) : NMI Է, up-edge sampleȴ. NMI ISR(Interrupt Service Routine) 203EH jumpѴ.

11. INST(Instruction) : , active High, CPU instruction ִٴ ǥϱ ȣ̴.

ܺ memory OP code fetchϴ "H" µȴ. resetĿ 2080H ִ OP code fetchϴ ȿ "H" ȴ.

reset 2018H ִ memory readؼ CCR , 2018H data̹Ƿ, "L" µȴ.

IVT(Interrupt Vector Table) read data̱ "L" µȴ.

read "L" µȴ.

** INST BUS cycle ȿϸ, ܺ memory accessϴ ȿ Ѵ.

* CCB (Chip Configuration Byte)

80C196KC Reset Ǹ, ó 2018H CCB readؼ CPU CCR(Chip Configuration Register) Ѵ. CCB chip ۿ ְ Ǵµ ̴ .

                  

12. (External Enable) : Է, ܺ/ ÿ ȴ.

=H ̸, 87C196KC 2000H~5FFFH ROM/EP-ROM õȴ.

=L ̸, ܺ ROM õȴ. 80C196KC ϴ Low ؾѴ.

13. BUSWIDTH : Է, 8/16bit external data bus width ÿ Ѵ.

CCR bit 1 "1"̸, bus cycle pin ° bus width Ѵ. BUSWIDTH=1̸ 16bit, 0̸ 8bit bus ȴ.

CCR bit 1 "0"̸, BUSWIDTH pin ׻ 8bit bus ȴ.

14. ALE/ (Address Latch Enable/Address Valid) : , CCR ALEǴ ϸ,      Address/Data bus address latchϱ ȣ ȴ.

CCR bit 3 "1"̸ ALE , "0"̸

** ALE/ ܺ memory accessϴ Ѵ.

15./ (Read) : , active "L", ܺ memory data б ؼ ϴ ȣ̴.

16. / (Write/Write Low) : , active "L", CCR /

CCR bit2 "1" ϸ ܺ memory data write Ѵ. ܺο / Ͽ /  ؾ Ѵ.

CCR bit2 "0" ܺ memory ¦ address data write Ѵ.

** / ܺ memory accessϴ ȿ Ѵ.

17. / (Bus High Enable/Write High) : , CCR

CCR bit2 "1" ȣ ϸ, data bus(D15~D8), Address bus A0 data bus(D7~D0) Ѵ. ,

BHE#

A0

D15~D8

D7~D0


1

0

No

active

even address(byte)

0

1

active

No

odd address(byte)

0

0

active

active

even address(byte)

 

CCR bit2 "0" Ǹ, odd address data write Ѵ./ 16bit data bus Ͽ write ȴ.

18. READY : Է, active "L", ܺ memory cycle ϱ ؼ Ѵ. , ܺ IO memory access bus cycle ϴµ Ѵ.

READY="H"̸ CPU wait state bus cycle ϰ, "L"̸ memory controller wait state ȴ. ܺ memory READYȣ , bus cycle ԵǴ wait READY ȣ ̿ ʰ, CCR bit 4,5 ̿ ִ.

19. HSI(High Speed Input) : Է pin, 4 HSI(HSI.0, HSI.1, HSI.2, HSI.3) ְ, HSI.2 HSI.3 HSO Բ ִ.

20. HSO(High Speed Output) : pin, 6 HSO(HSO.0, HSO.1, HSO.2, HSO.3, HSO.4, HSO.5) , HSO.4 HSO.5 HSI ִ.

21. port 0(P0.0/ACH0~P0.7/ACH7) : 8bit high-Z input port, port digital Ǵ analog ȣ Է(ADC)ϴ ȴ.

P0.0/ACH0~P0.7/ACH7 : digital/analog input

P0.4/ACH4/PMODE0~P0.7/ACH7/PMODE3 : digital/analog input/87C196KC EP-ROM write write mode

P0.7 EXINT1(external interrupt 1) ִ.

22. port 1(P1.0~P1.7) : 8bit (quasi-bidirectional) port, IO port Ѵ.

P1.0~P1.2 : IO port Ѵ.

P1.3/PWM1, P1.4/PWM2 : IO port PWM(Pulse Width Modulation) Ѵ.

P1.5/ , P1.6/ , P1.7/: IO port DMA(Direct Memory Access) Ѵ.

23. Port 2 : 8bit ٱ Ʈ : port2 ٸ ɵ multiplexǾ ִ.

IO port

multiplex ɵ

ٸ

SFR

P2.0/TXD

output

Transmit data(Serial)

IOC1.5

P2.1/RXD

input

Receive data(Serial)

SPCON.3

P2.2/EXINT

input

external interrupt input

IOC1.1

P2.3/T2CLK

input

Timer 2 clock & baud

IOC0.7

P2.4/T2RST

input

Timer 2 Reset

IOC0.5

P2.5/PWM0

output

PWM output

IOC1.0

P2.6/T2UP-DN

bi-directional

Timer 2 up/down select

IOC2.1

P2.7/T2CAP

bi-directional

Timer 2 capture

N/A

 

87C196KC EP-ROM write ȣ ȴ.

24. Port 3/4 : 8bit bi-directional port(open drains), port ܺ memory accessÿ address/data bus Ѵ.(ο pullup ִ.)

AD0/P3.0~AD7/P3.7 : address/data bus AD0~AD7

AD8/P4.0~AD15/P4.7 : address/data bus AD8~AD15

: http://www.postech.ac.kr/group/poweron/ - lectures/Micro processor, controller, Ƹ

                         : Micro controller 80196 ʺ -



 

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